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for pricing, delivery, and ordering information, plea se contact maxim direct at 1- 888 - 629 - 4642, or visit maxim integrateds website at www.maximintegrated.com. 19 - 5375; rev 2; 10 / 13 71m6543f/71m6543g energy meter ics general description the 71m6543f / 71m6543 g are 4 th - generation pol y phase metering system s- on - chips ( so c s) with a 5mhz 8051 - compatib le mpu core, low - power real - time clock ( rtc ) with digital temperature compensation, f lash memory , and lcd driver. our single con verter technology ? with a 22 - bit delta - sigma adc, seven analog inputs, digital metrology temperature compensation, precision vol tage reference , and a 32 - bit computation engine (ce) supports a wide range of metering applications with very few external components. the 71m6543f / 71m6543 g support optional interfaces to the 71m6xx 3 series of i solated s ensors that offer bom cost reduction, immunity to magnetic tamper , and enhanced reliability . the ics feature ultra - low - power operation in active and battery modes , 5kb shared ram , and 64kb (71m6543f) or 128kb (71m6543g) of f lash memory , which can be pro grammed with code and/or data during meter operation. a complete array of code development tools, demonstration code , and reference designs enable rapid development and certification of meters that meet all ansi and iec electricity metering standards worldwide. mpu rtc timers iadc0 vadc 8 ( va ) iadc 2 vadc9 (vb) xin xout rx tx txrx com0...5 v3p3a v3p3 sys vbat vbat_rtc iadc 4 vadc10 (vc) seg gnda gndd seg/dio dio ice c ba neutral load 8888.8888 pulses, dio ir amr power fault comparator modul- ator serial ports oscillator/ pll mux and adc lcd driver dio, pulses compute engine flash memory ram 32 khz regulator shunt current sensors power supply 71m6543f/ 71m6543g temperature sensor vref iadc 6 battery pwr mode control wake-up neutral i 2 c or wire eeprom 9/17/2010 iadc1 iadc 3 iadc 5 iadc 7 rtc battery v3p3d battery monitor spi interface host lcd display resistor dividers pulse transformers 3x 71m6xx3 note: this system is referenced to neutral 71m6xx371m6xx3 71m6xx3 } in* } ia } ib } ic *in = neutral current features ? 0.1% typical accuracy ov er 2000:1 current ran ge ? exceeds iec 62053/ansi c12.20 s tandards ? seven sensor inputs with neutral current measurement, differential mode selectab le for current inputs ? selectable g ain of 1 or 8 for o ne c urrent i nput to s upport s hunts ? high -s peed wh/varh p ulse o utputs with p rogrammable w idth ? 64kb flash, 5kb ram (71m6543f) ? 128kb flash, 5kb ram (71m6543g) ? up to f our p ulse o utputs with p ulse co unt ? four -q uadrant m etering, p hase s equencing ? digital t emperature c ompensation : me trology c ompensation accurate rtc for tou f unctions with a utomatic t emperature c ompensation for c rystal in a ll p ower m odes ? independent 32 -b it c ompute e ngine ? 46- 64 hz l ine f requency r ange with the s ame c alibration ? p hase c ompensation ( 7 ) ? three b attery -b ackup m odes: brownout m ode lcd m ode sleep m ode ? wake -u p on p in e vents and wake - on - timer ? 1 a in sleep m ode ? flash security ? in -s ystem p rogram u pdate ? 8-b it mpu (80515), u p to 5 m ips ? full -s peed mpu c lock in b rownout m ode ? lcd driver: 6 common s egment d rivers up to 56 s electable p ins ? up to 51 m ultifunction dio p ins ? hardware watchdog time r (wdt) ? i 2 c/m icrowire ? eeprom interface ? spi i nterface with flash program capabi lity ? two uarts for ir and amr ? ir led driver with m odulation ? industrial temperature range ? 100 - pin lead - free lqfp p ackage single converter technology is a registered trademark of maxim integrated products, inc. microwire is a registered trademark of national semiconductor corp. downloaded from: http:///
71m6543f/71m6543g data sheet 2 v2 table of contents 1 introduction ....................................................................................................................................... 10 2 hardware description ....................................................................................................................... 11 2.1 hardware overview ................................................................................................................... 11 2.2 analog front - end (afe) ............................................................................................................ 12 2.2.1 signal input pins ............................................................................................................ 13 2.2.2 input multiplexer ............................................................................................................. 14 2.2.3 delay compensation ..................................................................................................... 19 2.2.4 adc pre - amplifier ......................................................................................................... 20 2.2.5 a/d converter (adc) ..................................................................................................... 20 2.2.6 fir filter ........................................................................................................................ 20 2.2.7 voltage references ....................................................................................................... 20 2.2.8 71m6xx3 isolated sensor interface ............................................................................... 22 2.3 digital computation engine (ce) ............................................................................................... 25 2.3.1 ce program memory ..................................................................................................... 25 2.3.2 ce data memory ........................................................................................................... 25 2.3.3 ce communication with the mpu ................................................................................. 25 2.3.4 meter equations ............................................................................................................. 26 2.3.5 real - time monitor (rtm) .............................................................................................. 26 2.3.6 pulse generators ........................................................................................................... 26 2.3.7 ce functional overview ................................................................................................ 28 2.4 80515 mpu core ....................................................................................................................... 30 2.4.1 memory organization and addressing .......................................................................... 30 2.4.2 special function registers (sfrs) ................................................................................ 32 2.4.3 generic 80515 special function registers ................................................................... 33 2.4.4 instruction set ................................................................................................................ 35 2.4.5 uarts ........................................................................................................................... 35 2.4.6 timers and counters ..................................................................................................... 38 2.4.7 wd timer (software watchdog timer) ......................................................................... 39 2.4.8 interrupts ........................................................................................................................ 39 2.5 on - chip resources ................................................................................................................... 46 2.5.1 physical memory ............................................................................................................ 46 2.5.2 oscillator ........................................................................................................................ 48 2.5.3 pll and internal clocks ................................................................................................ . 49 2.5.4 real - time clock (rtc) ................................................................................................ . 49 2.5. 5 71m6543 temperature sensor ...................................................................................... 53 2.5.6 71m6xx3 temperature sensor ...................................................................................... 56 2.5.7 71m6543 battery monitor .............................................................................................. 56 2.5.8 71m6xx3 vcc monitor ................................................................................................... 56 2.5.9 uart and optical interface ........................................................................................... 56 2.5.10 digital i/o and lcd segment drivers ............................................................................ 57 2.5.11 eeprom interface ........................................................................................................ 65 2.5.12 spi slave port ................................................................................................................ 67 2.5.13 hardware watchdog timer ............................................................................................ 71 2.5.14 test ports (tmuxout and tmux2out pins) ............................................................. 72 3 functional description ..................................................................................................................... 74 3.1 theory of operation ................................................................................................................... 74 3.2 battery modes ............................................................................................................................ 74 3.2.1 brn mode ..................................................................................................................... 77 downloaded from: http:///
71m6543f/71m6543g data sheet v2 3 3.2.2 lcd mode ...................................................................................................................... 77 3.2.3 slp mode ...................................................................................................................... 78 3.3 fault and reset behavior .......................................................................................................... 79 3.3.1 events at power - down .................................................................................................. 79 3.3.2 ic behavior at low battery voltage ............................................................................... 80 3.3.3 reset sequence ............................................................................................................ 80 3.3.4 watchdog timer (wdt) reset ...................................................................................... 80 3.4 wake - up behavior ..................................................................................................................... 81 3.4.1 wake on hardware events ............................................................................................ 81 3.4.2 wake on timer ............................................................................................................... 83 3.5 data flow and mpu/ce communication ................................................................................... 83 4 application information .................................................................................................................... 85 4.1 connecting 5 v devices ............................................................................................................. 85 4.2 di rectly connected sensors ...................................................................................................... 85 4.3 systems using 71m6xx3 isolated sensors and current shunts ............................................... 86 4.4 system using current transformers ......................................................................................... 87 4.5 metrology temperature compensation ..................................................................................... 88 4.5.1 temperature compensation .......................................................................................... 88 4.5.2 temperature coefficients for the 71m6543f and 71m6543g ....................................... 88 4.5.3 temperature coefficients for the 71m6xx3 ................................................................... 89 4.5.4 temperature compensation for vref and shunt sens ors .......................................... 89 4.5.5 temperature compensation of vref and current transformers ................................ . 90 4.6 connecting i 2 c eeproms ........................................................................................................ 92 4.7 connecting three - wire eeproms ........................................................................................... 92 4.8 uart0 (tx/rx) ......................................................................................................................... 92 4.9 optical interface (uart1) .......................................................................................................... 93 4.10 connecting the reset pin .......................................................................................................... 93 4.11 connecting the emulator port pins ............................................................................................ 94 4.12 flash programming .................................................................................................................... 94 4.12.1 flash programming via the ice port ............................................................................. 94 4.12.2 flash programming via the spi port ............................................................................. 94 4.13 mpu demonstration code ......................................................................................................... 94 4.14 crystal oscillator ........................................................................................................................ 95 4.15 meter calibration ........................................................................................................................ 95 5 firmware interface ............................................................................................................................ 96 5.1 i/o ram map C functional order ............................................................................................... 96 5.2 i/o ram map C alphabetical order ......................................................................................... 102 5.3 ce interface description .......................................................................................................... 116 5.3.1 ce program ................................................................................................................. 116 5.3.2 ce data format ........................................................................................................... 116 5.3.3 constants ..................................................................................................................... 116 5.3.4 environment ................................................................................................................. 117 5.3.5 ce calcu lations ........................................................................................................... 117 5.3.6 ce front - end data (raw data) ................................................................................... 118 5.3.7 ce status and control ................................................................................................ . 119 5.3.8 ce transfer variables ................................................................................................ . 121 5.3.9 pulse generation ......................................................................................................... 123 5.3.10 ce calibration parameters .......................................................................................... 127 5.3.11 ce flow diagrams ....................................................................................................... 128 downloaded from: http:///
71m6543f/71m6543g data sheet 4 v2 6 71m6543 specifications .................................................................................................................. 130 6.1 absolute maximum ratings ..................................................................................................... 130 6.2 recommended external components ..................................................................................... 131 6.3 recommended operating conditions ...................................................................................... 131 6.4 performance specifications ..................................................................................................... 132 6.4.1 input logic levels ........................................................................................................ 132 6.4.2 output logic levels ..................................................................................................... 132 6.4.3 battery monitor ............................................................................................................. 133 6.4.4 temperature monitor ................................................................................................... 134 6.4.5 supply current ............................................................................................................. 135 6.4.6 v3p3d switch .............................................................................................................. 136 6.4.7 internal power fault comparators ............................................................................... 136 6.4.8 2.5 v voltage regulator C system power ................................................................... 136 6.4.9 2.5 v voltage regulator C battery power .................................................................... 137 6.4.10 crystal oscillator .......................................................................................................... 137 6.4.11 phase - locked loop (pll) ........................................................................................... 137 6.4.12 lcd drivers ................................................................................................................. 137 6.4.13 vlcd generator .......................................................................................................... 138 6.4.14 71m6543 vref ........................................................................................................... 140 6.4.15 adc converter ............................................................................................................. 141 6.4.16 pre - amplifier for iadc0 - iadc1 ................................................................................... 142 6.5 timing specifications ............................................................................................................... 143 6.5.1 flash memory .............................................................................................................. 143 6.5.2 spi sl ave ..................................................................................................................... 143 6.5.3 eeprom interface ...................................................................................................... 143 6.5.4 reset pin ................................................................................................................... 144 6.5.5 real - time clock (rtc) ............................................................................................... 144 6.6 100 - pin lqfp package outline drawing ................................................................................ 145 6.7 71m6543 pinout ....................................................................................................................... 146 6.8 71m6543 pin descriptions ....................................................................................................... 147 6.8.1 71m6543 power and ground pins .............................................................................. 147 6.8.2 71m6543 analog pins .................................................................................................. 148 6.8.3 71m6543 digital pins ................................................................................................... 149 6.8.4 i/o equivalent circuits ................................................................................................ . 151 7 ordering information ...................................................................................................................... 152 7.1 71m6543 ordering guide ........................................................................................................ 152 8 related information ..................................................................................................................... 152 9 contact information ..................................................................................................................... 152 appendix a: acronyms .......................................................................................................................... 153 appendix b: revision history ................................................................................................................ 154 downloaded from: http:///
71m6543f/71m6543g data sheet v2 5 figures figure 1: ic functional block diagram ......................................................................................................... 9 figure 2: afe block diagram (shunts: one - local, three - remotes) ......................................................... 12 figure 3. afe block diagram (four cts) ................................................................................................... 13 figure 4: states in a multiplexer frame ( mux_div[3:0] = 6) ..................................................................... 17 figure 5: states in a multiplexer frame ( mux_div[3:0] = 7) ..................................................................... 17 figure 6: general topology of a chopped amplifier .................................................................................. 21 figure 7: cross signal with chop_e = 00 ............................................................................................... 21 figure 8: rtm timing ................................................................................................................................ . 26 figure 9. pulse generator fifo timing ...................................................................................................... 28 figure 10: samples from multiplexer cycle (frame) .................................................................................. 29 figure 11: accumulation interval ................................................................................................................ 29 figure 12: interrupt structure ...................................................................................................................... 45 figure 13: automatic temperature compensation ..................................................................................... 52 figure 14: optical interface ......................................................................................................................... 57 figure 15: optical interface (uart1) ......................................................................................................... 57 figure 16: connecting an external load to dio pins ................................................................................. 59 figure 17: lcd waveforms ......................................................................................................................... 64 figure 18: 3 - wire interface. write command, hiz=0. ................................................................................ 66 figure 19: 3 - wire interface. write command, hiz=1 ................................................................................. 67 figure 20: 3 - wire interface. read command. ............................................................................................ 67 figure 21: 3 - wire interface. write command when cnt=0 ...................................................................... 67 figure 22: 3 - wire interface. write command when hiz=1 and wfr=1. ................................................... 67 figure 23: spi slave port - typical multi - byte read and write operations ................................................ 69 figure 24: voltage, current, momentary and accumulated energy ........................................................... 74 figure 25: operation modes state diagram ............................................................................................... 75 figure 26: mpu/ce data flow .................................................................................................................... 84 figure 27: resistive voltage divider (voltage sensing) ............................................................................. 85 figure 28. ct with single - ended input connection (current sensing) ...................................................... 85 figure 29: ct with differential input connection (current sensing) .......................................................... 85 figure 30: differential resistive shunt connections (current sensing) ..................................................... 85 figure 31: system using three - remotes and one - local (neutral) sensor .............................................. 86 figure 32. system using current transformers ......................................................................................... 87 figure 33: i 2 c eeprom connection .......................................................................................................... 92 figure 34: connections for uart0 ............................................................................................................. 92 figure 35: connection for optical components .......................................................................................... 93 figure 36: external components for the reset pin: push - button (left), production circuit (right) ........ 94 figure 37: external components for the emulator interface ...................................................................... 94 figure 38: ce data flow: multiplexer and adc ........................................................................................ 128 figure 39: ce data flow: scaling, gain control, intermediate variables for one phase ......................... 128 figure 40: ce data flow: squaring and summation stages .................................................................... 129 figure 41: 100 - pin lqfp package outline ............................................................................................... 145 figure 42: pinout for the lqfp - 100 package ........................................................................................... 146 figure 43: i/o equivalent circuits ............................................................................................................. 151 downloaded from: http:///
71m6543f/71m6543g data sheet 6 v2 tables table 1. required ce code and settings for 1 - local / 3 - remotes ............................................................ 15 table 2. required ce code and settings for ct sensors ......................................................................... 16 table 3: multiplexer and adc configuration bits ........................................................................................ 19 table 4. rcmd[4:0] bits ............................................................................................................................. 23 table 5: remote interface read commands ............................................................................................. 23 table 6: i/o ram control bits for isolated sensor ..................................................................................... 24 table 7: inputs selected in multiplexer cycles ........................................................................................... 26 table 8: ckmpu clock frequencies .......................................................................................................... 30 table 9: memory map ................................................................................................................................ . 31 table 10: internal data memory map ......................................................................................................... 32 table 11: special function register map ................................................................................................... 32 table 12: generic 80515 sfrs - location and reset values .................................................................... 33 table 13: psw bit functions (sfr 0xd0) ................................................................................................... 34 table 14: port registers (segdio0 - 15) ..................................................................................................... 35 table 15: stretch memory cycle width ...................................................................................................... 35 table 16: baud rate generation ................................................................................................................ 36 table 17: uart modes ............................................................................................................................... 36 table 18: the s0con (uart0) register (sfr 0x98) ................................................................................. 37 table 19: the s1con (uart1) register (sfr 0x9b) ................................................................................ 37 table 20: pcon register bit description ( sfr 0x87 ) ................................................................................. 38 table 21: timers/counters mode description ............................................................................................ 38 table 22: allowed timer/counter mode combinations .............................................................................. 38 table 23: tmod register bit description (sfr 0x89) ................................................................................ 39 table 24: the tcon register bit functions (sfr 0x88) ............................................................................ 39 table 25: the ien0 bit functions (sfr 0xa8) ............................................................................................ 40 table 26: the ien1 bit functions (sfr 0xb8) ............................................................................................ 40 table 27: the ien2 bit functions (sfr 0x9a) ............................................................................................ 41 table 28: tcon bit functions (sfr 0x88) ................................................................................................ . 41 table 29: the t2con b it functions (sfr 0xc8) ........................................................................................ 41 table 30: the ircon bit functions (sfr 0xc0) ........................................................................................ 41 table 31: external mpu interrupts .............................................................................................................. 42 table 32: interrupt enable and flag bits .................................................................................................... 42 table 33: interrupt priority level groups .................................................................................................... 43 table 34: interrupt priority levels ............................................................................................................... 43 table 35: interrupt priority registers ( ip0 and ip1 ) .................................................................................... 43 table 36: interrupt polling sequence .......................................................................................................... 44 table 37: interrupt vectors .......................................................................................................................... 44 table 38: flash memory access ................................................................................................................. 46 ta ble 39: bank switching with fl_bank[1:0] (sfr 0xb6[1:0]) in the 71m6543g ....................................... 47 table 40: flash security ............................................................................................................................. 48 table 41: clock system summary .............................................................................................................. 49 ta ble 42: rtc control registers ................................................................................................................ 50 table 43: i/o ram registers for rtc temperature compensation .......................................................... 52 table 44: i/o ram registers for rtc interrupts ........................................................................................ 53 table 45: i/o ram registers for temperature and battery measurement ................................................ 55 table 46: selectable resources using the dio_rn[2:0] bits ..................................................................... 58 table 47: data/direction registers and internal resources for segdio0 to s egdio15 ......................... 60 table 48: data/direction registers for segdio16 to segdio31 .............................................................. 60 downloaded from: http:///
71m6543f/71m6543g data sheet v2 7 table 49: data/direction registers for segdio32 to segdio45 .............................................................. 60 table 50: data/direction registers for segdio51 to segdio55 .............................................................. 61 table 51: lcd_vmode configurations ...................................................................................................... 61 table 52: lcd configurations ..................................................................................................................... 63 table 53: lcd data registers for segdio46 to segdio55 ..................................................................... 64 table 54: eectrl bits for 2 - pin interface ................................................................................................... 65 table 55: eectrl bits for the 3 - wire interface ........................................................................................... 66 table 56: spi transaction fields ................................................................................................................ 68 table 57: spi command sequences .......................................................................................................... 69 table 58: spi registers .............................................................................................................................. 69 table 59: tmux[4:0] selections ................................................................................................................. 72 table 60: tmux2[4:0] selections ............................................................................................................... 73 table 61: available circuit functions .......................................................................................................... 76 table 62: vstat[2:0] (sfr 0xf9[2:0]) ........................................................................................................ 79 table 63: wake enable and flag bits ......................................................................................................... 81 table 64: wake bits .................................................................................................................................... 82 table 65: clear events for wake flags ...................................................................................................... 83 table 66: gain_adjn compensation channels (figure 2, figure 31, table 1) ........................................ 90 table 67: gain_adjx compensation channels (figure 3, figure 32, table 2) ........................................ 91 table 68: i/o ram map C functional order, basic configuration .............................................................. 96 table 69: i/o ram map C functional order ............................................................................................... 98 table 70: i/o ram map C alphabetical order .......................................................................................... 102 table 71: ce equ[2:0] equations and element input mapping ............................................................... 117 table 72: ce raw data access locations ............................................................................................... 118 table 73: cestatus register ................................................................................................................... 119 table 74: cestatus bit definitions .......................................................................................................... 119 table 75: ceconfig register .................................................................................................................. 119 tabl e 76: ceconfig bit definitions (ce ram 0x20) ............................................................................... 120 table 77: sag threshold, phase measurement, and gain adjust control ............................................... 121 table 78: ce transfer variables (with shunts) ......................................................................................... 121 table 79: ce transfer variables (with cts) ............................................................................................. 122 table 80: ce energy measurement variables (with shunts) ................................................................... 122 table 81: ce energy measurement variables (with cts) ........................................................................ 122 table 82: other transfer variables ........................................................................................................... 123 table 83: ce pulse generation parameters ............................................................................................. 125 table 84: ce parameters for noise suppression and code version ....................................................... 126 table 85: ce calibration parameters ....................................................................................................... 127 table 86: absolute maximum ratings ...................................................................................................... 130 table 87: recommended external components ...................................................................................... 131 table 88: recommended operating conditions ....................................................................................... 131 table 89: input logic levels ..................................................................................................................... 132 table 90: output logic levels .................................................................................................................. 132 table 91: battery monitor performance specifications ( temp_bat = 1) ................................................. 133 table 92: temperature monitor ................................................................................................................ 134 table 93: supply current performance specifications ............................................................................. 135 table 94: v3p3d switch performance specifications .............................................................................. 136 table 95: internal power fault comparators performance specifications ............................................... 136 table 96: 2.5 v voltage regulator performance specifications ............................................................... 136 table 97: low - power voltage regulator performance specifications ..................................................... 137 table 98: crystal oscillator performance s pecifications .......................................................................... 137 downloaded from: http:///
71m6543f/71m6543g data sheet 8 v2 table 99: pll performance specifications ............................................................................................... 137 table 100: lcd drivers performance specifications ............................................................................... 137 table 101: vlcd generator specifications .............................................................................................. 138 table 102: 71m6543 vref performance specifications ......................................................................... 140 table 103: adc converter performance specifications ........................................................................... 141 table 104: pre - amplifier performance specifications .............................................................................. 1 42 table 105: flash memory timing specifications ...................................................................................... 143 table 106. spi slave timing specifications ............................................................................................. 143 table 107: eeprom interface timing ...................................................................................................... 143 table 108: reset pin timing .................................................................................................................. 144 tabl e 109: rtc range for date ............................................................................................................... 144 table 110: 71m6543 power and ground pins .......................................................................................... 147 table 111: 71m6543 analog pins ............................................................................................................. 148 table 112: 71m6543 digital pins .............................................................................................................. 149 table 113. 71m6543 ordering guide ....................................................................................................... 152 downloaded from: http:///
71m6543f/71m6543g data sheet v2 9 figure 1 : ic functional block diagram iadc 0 mux and preamp xin xout vref ckadc ce 32 - bit compute engine mpu ( 80515 ) ce control opt _ rx / segdio 55 opt _ tx / segdio 51 / wpulse / vpulse reset vbias emulator port 3 c e _ b u s y optical interface uart 0 tx rx x f e r b u s y 6 com 0 .. 5 vlc 2 lcd driver cedata 0 x 000 ... 0 x 2 ff prog 0 x 000 ... 0 x 3 ff data 0 x 0000 ... 0 xffff program 0 x 0000 ... 0 xffff 0 x 00000 0 x1ffff digital i / o configuration ram ( i / o ram ) 0 x 2000 ... 0 x 20 ff i / o r a m memory share 0 x 0000 ... 0 x 13 ff 16 8 rtclk rtclk ( 32 khz ) mux _ sync ckce ckmpu ck 32 32 8 8 8 power fault detection 4 . 9 mhz < 4 . 9 mhz 4 . 9 mhz gndd v 3 p 3 a v 3 p 3 d vbat voltage regulator 2 . 5 v to logic vdd 32 khz mpu _ rstz faultz wake con - figuration parameters gnda vbias 9 / 20 / 2010 cross clock gen oscillator 32 khz ck 32 mck pll vref div adc mux ctrl strt mux mux ckfir rtm segdio pins wpulse varpulse wpulse varpulse test test mode vlc 1 vlc 0 < 4 . 9 mhz ckmpu _ 2 x ckmpu _ 2 x sdck sdout sdin e _ rxtx / seg 48 e _ tclk / seg 49 e _ rst / seg 50 flash 128 kb v 3 p 3 a fir eeprom interface ck _ 4 x lcd _ gen pb rtc vbias memory share 17 e _ rxtx e _ tclk e _ rst ( open drain ) ice _ e ?_ ad converter + - vref v 3 p 3 sys test mux vlcd vlcd voltage boost mpu ram ( 5 kb ) 22 s p i vstat vbat _ rtc iadc 1 iadc 2 iadc 3 iadc 4 iadc 5 iadc 6 iadc 7 vadc 8 ( va ) vadc 9 ( vb ) vadc 10 ( vc ) seg pins 2 test mux 2 non - volatile configuration ram bat test temp sensor rtm downloaded from: http:///
71m6543f/71m6543g data sheet 10 v2 1 introduction this data sheet covers the 71m6543f ( 64kb ) and 71m6543g (128kb) 4th - generation polyphase energy measurement system - on - chips ( socs ) . the term 71m6543 is used when discussing a device feature or behavior that is applicable to all four part numbers. the specific part numbers are used when discussing those features that apply only to specific part numbers. this data sheet also covers details about the companion 71m6xx3 isolated current sensor device. this document covers the use of the 71m6543 in conjunction with the 71m6xx3 isolated current sensor. the 71m6543 and 71m6xx3 ics make it possible to use one non - isolated and three additional isolated s hunt current sensors to create polyphase energy meters using inexpensive shunt resistors, while achieving unprecedented performance with this type of sensor technology. the 71m6543 socs also support current transformers (ct). to facilitate document navigation, hyperlinks are often used to reference figures, tables and section headings that are located in other parts of the document. all hyperlinks in thi s document are highlighted in blue . hyperlinks are used extensively to increase the level of detail and clarity provided within each section by referencing other relevant parts of the document. to further facilitate document navigation, this document is published as a pdf document with bookmarks enabled. the reader is also encouraged to obtain and review the documents listed in 8 related information on page 152 of this document. downloaded from: http:///
71m6543f/71m6543g data sheet v2 11 2 hardware description 2.1 hardware overview the 71m6543 single - chip energy meter integrate s all primary functional blocks re quired to implement a solid - state electricity meter. included on the chip are : ? an a nalog front - end (afe) featuring a 22 - bit second - order sigma - delta adc ? an i ndependent 32 - bit digital computation engine (ce) to implement dsp functions ? an 8051 - compatible microprocessor (mpu) which executes one instruction per clock cycle (80515) ? a precision voltage reference (vref) ? a temperature sensor for digital temperature compensation of : - metrology (mpu) - automatic rtc in all power states - mpu assisted rtc compensation ? lcd driver ? ram and flash memory ? a real time clock (rtc) ? a variety of i/o pi ns ? a power failure interrupt ? a zero - crossing interrupt ? selectable current sensor interfaces for locally - connected sensors as well as i solated sensors ( i.e., using the 71m6xx3 companion ic with a shunt resistor sensor ) ? resistive shunt and cur rent transformers are supported in order to implement a polyphase meter with or without neutral current sensing, one resistive shunt cur rent sensor m ay be connected directly (non - isolated) to the 71m6543 device, while up to three additional current shunts are isolated using a companion 71m6xx3 isolated sensor ic. an inexpensive, small size pulse transformer is used to electrically isolate the 71m6xx3 remote sensor from the 71m6543. the 71m6543 performs digital communications bi - directionally with the 71m6xx3 and also provides power to the 71m6xx3 through the isolating pulse transformer. isolated (remote) shunt current sensors are connected to the differ ential input of the 71m6xx3. the 71m6543 may also be used with current transformers; in this case the 71m6xx3 isolated sensors are not required. included on the 71m6xx3 companion isolator chip are: ? digital isolation communications interface ? an a nalog front - end (afe) featuring a 22 - bit second - order sigma - delta adc ? a precision voltage reference (vref) ? a temperature sensor (for current - sensing digital temperature compensation) ? a fully differential shunt resistor sensor input ? a pre - amplifier to optimize shunt current sensor performance ? isolated power circuitry obtains dc power from pulses sent by the 71m6543 in a typical application, the 32 - bit compute engine (ce) of t he 71m6543 sequentially processes the samples from the voltage inputs on analog input pins and performs calculations to measure active ener gy (wh) and reactive energy (varh), as well as a 2 h, and v 2 h for four - quadrant metering. these measurements are then accessed by the mpu, processed further and output using the peripheral devices available t o the mpu. in addition to advanced measurement functions, the real time clock (rtc) function allows the 71m6543 to record time of use (tou) metering information for multi - rate applications and to time - stamp tamper or other events. a n automatic rtc temperat ure compensation circuit operates in all power states including when the mpu is halted, and continues to compensate using back - up battery power during power outages. measurements can be displayed on 3.3 v lcds commonly used in low - temperature environments . the integrated charge pump and temperature sensor can be used by the mpu to enhance 3.3 v lcd performance at cold temperatures. the on - chip charge pump may also drive 5 v lcds. flexible mapping of lcd display segments facilitate s the integration of existing custom lcds. design trade - off between the downloaded from: http:///
71m6543f/71m6543g data sheet 12 v2 number of lcd segments and dio pins can be implemented in software to accommodate v arious requirements. in addition to the temperature - trimmed ultra - precision voltage reference, the on - chip digital temperature com pensation mechanism includes a temperature sensor and associated controls for correct ion of unwanted temperature effects on metrology and rtc accuracy (i.e., to meet the requirements of ansi and iec standards ). temperature - dependent external components such as the crystal oscillator , current transformers (cts) , current shunts and their corresponding signal conditioning circuits can be character - ized and their correction factors can be programmed to produce electri city meters with exceptional accuracy over the indus trial temperature range. one of the two internal uarts is adapted to support an infrared l ed with interna l drive and sense confi guration and can also function as a standard uart. the optical output can be modulated at 38 k hz. this flexibility makes it possible to implement amr meters with an ir interface. a block diagram of the ic is shown in figure 1 . 2.2 analog front - end (afe) the afe functions as a data acquisition system, controlled by the mpu. the 71m6543 afe may also be augmented by isolated 71m6xx3 sensors in order to support low - cost current shunt sensors. figure 2 , and figure 3 show the two most common configurations; other configurations are possible. sensors that are connected directly to the 71m6543 (i.e., ia dc0 - ia dc1 , va dc8 , v adc9 and v adc10 ) are multiplexed in t o the single second - order sigma - delta adc input for sam pling in the 71m6543 . the 71m6543 adc output is decimated by the fir filter and stored in ce ram where it can be accessed and processed by the ce. shunt current sensors that are isolated by using a 71m6xx3 device, are sam pled by a second - order sigma delta adc in the 71m6xx3 and the signal samples are transferred over the digital isolation inter face through the low - cost isolation pulse transformer. figure 2 show s the 71m6543 us ing shunt current sensors and the 71m6xx3 isolated sensor device s . figure 2 supports neutral current measurement with a local shunt connected to the ia dc0 - iadc1 input plus three remote (isolated) shunt sensors. as seen in figu re 2 , when a remote isolated shunt sensor is connected via the 71m6x x3 , the samples associated with this current channel are not routed to the multiplexer, and are instead transferred digitall y to the 71m654 3 via the isolation interface and are directly stored in ce ram. the mux_sel n [3:0] i/o ram control fields allow the mpu to configure the afe for the desired multiplexer sampling sequence. refer to tab le 1 and table 2 for the appropriate ce code and the corresponding afe settings. see figure 31 for the meter wiring configuration corresponding to figure 2 . ? adc converter vref mux vref vref vadc 22 fir iadc 2 vadc9 (vb) iadc0 vadc8 (va) iadc1 iadc 3 71m6543 ce ram 71m6xx3 sp sn inp inn remote shunt ib digital isolation interface local shunt in* 22 iadc 4 iadc 5 71m6xx3 sp sn inp inn remote shunt ic vadc10 (vc) 22 iadc 6 iadc 7 71m6xx3 sp sn inp inn remote shunt ia 22 *in = neutral current 9/17/2010 figure 2 : afe block diagram (shunts: one - local, three - remotes) downloaded from: http:///
71m6543f/71m6543g data sheet v2 13 the 71m6543 afe can also be directly interfaced to current transformers (cts), as seen in figure 3 . in this case, all voltage and current channels are multiplexed into a single second - order sigma - delta adc in the 71m6543 and the 71m6xx3 remote isolated sensors are not used. the fourth ct and the measureme nt of neutral current via the iadc0 - iadc1 current channel are optional. see figure 32 for the meter wiring configuration corresponding to figure 3 . ? adc converter vref mux vref vref vadc 22 fir iadc 4 vadc9 (vb) iadc2 vadc8 (va) iadc3 iadc 5 71m6543 ce ram ib ct ia ct iadc 6 iadc 7 ic ct iadc 0 iadc 1 in* ct vadc10 (vc) 9/17/2010 *in = neutral current figure 3 . afe block diagram (four cts) 2.2.1 signal input pins the 71m6543 features eleven adc input pins. iadc0 through iadc7 are intended for use as current sensor inputs. these eight current sensor inputs can be configured as fou r single - ended inputs, or can be paired to form four differential inputs. for best performance, it is recommended to configure the current sensor inputs as di fferential inputs (i.e., iadc0 - iadc1, iadc2 - iadc3, iadc4 - iadc5 and iadc6 - iadc7). the first differential input (iadc0 - iadc1) features a pre - amplifier with a selectable gain of 1 or 8, and is intended for direct c onnection to a shunt resistor sensor, and can also be used with a current transformer (ct) . the three remaining differential pairs (i.e., iadc2 - iadc3, iadc4 - iadc5 and iadc6 - iadc7) may be used with cts, or may be enabled to interface to a remote 71m6x x 3 isolated current sensor providing isolation for a shunt resistor sensor using a low cost pulse transformer. the remaining three inputs vadc 8 (va), vadc 9 (vb) and vadc10 (vc) are single - ended, and are intended for sensing each of the phase voltages in a polyphase meter application. these three single - ended inputs are referenced to the v3p3a pin. all adc input pins measure voltage. in the case of shunt current sensors, currents are sense d as a voltage drop in the shunt resistor sensor. in the case of current transformers (ct), the current is measured as a voltage across a burden resistor that is connected to the secondary of the ct. meanwhile, line voltages are sensed through resistive voltage dividers. the vadc8 (va) , vadc9 (vb) and vadc10 (vc) pins are single - ended and their common return is the v3p3a pin. see figure 27 , figure 28 , figure 29 and figure 30 for detailed connections for each type of sensor. also refer to the 71m6543 demonstration board schematic and bill of materials for typical component values used in these and other circuits. downloaded from: http:///
71m6543f/71m6543g data sheet 14 v2 pins iadc0 - iadc1 can be programmed individually to be differential or single - ended as determined by the diff0 _e ( i /o ram 0x210c[4] ) control bit. however, for most applications, iadc0 - iadc1 are configured as a differential input to work with a resistive shunt or ct directly interfaced to the iadc0 - iadc1 differential input with the appropriate external signal conditioni ng components. the performance of the iadc0 - iadc1 pins can be enhanced by enabling a pre - amplifier with a fixed gain of 8, using the i/o ram control bit pre_e (i/o ram 0x2704[5]) . when pre_e = 1, iadc0 - iadc1 become the inputs to the 8x pre - amplifier, and the output of this amplifier is supplied to the multiplexer . the 8x amplification is useful when current sensors with low sensitivity, such as shunt resistors, are used. with pre_e set, the iadc0 - iadc1 input signal amplitude is restricted to 31.25 mv peak. when pre_e = 0 (gain = 1), the iadc0 - iadc1 input signal is restricted to 250 mv peak. for the 71m6543 application utilizing shunt resistor sensors ( figure 2 ), the iadc0 - iadc1 pins are configured for differential mode to interface to a local shunt by sett ing the diff0 _e control bit. meanwhile, the iadc2 - iadc3 , iadc4 - iadc5 and iadc6 - iadc7 pins are re - configured as digital remote sensor interface designed to communicate wi th a 71m6xx3 i solated s ensor by setting the rmt x _e control bits ( i/o ram 0x2709[ 5: 3] ). the 71m6x x3 communicate s with the 71m654 3 using a bi - directional digital data stream through an isolating pulse transformer. the 71m654 3 also supplies power to the 71m6x x3 through the isolating transformer. this type of interface is further described at the end of this chapter . s ee 2.2.8 71m6xx3 isolated sensor interface . for use with current transformers (cts), as shown in figure 3 , the rmtx_e control bits are reset, so that iadc2 - iadc3 , iadc4 - iadc5 and iadc6 - iadc7 are configured as local analog inputs. the iadc0 - iadc1 pin s cannot be configured as a remote sensor interface. 2.2.2 input multiplexer when operating with locally connected sensors, t he input multiplexer sequentially applies the input signals from the analog input pins to the input of the adc (see figure 3 ) , according to the sampling sequence determined by the eleven muxn_sel[3:0] control fields . one complete sampling sequence is called a multiplexer frame. the multiplexer of the 71m654 3 can select up to eleven input signal s when the current sensor input s are configured for single - ended mode. when the current sensor inputs are configured in differential mode (recommended for best performance), the number of input signals is seven (i.e., ia dc0 - ia dc1 , i adc2 -i adc3 , i adc4 -i adc5 , i adc6 -i adc7 , va dc8 , v adc9 and v adc10 ) per multiplexer frame . the number of slots in the multiplexer frame is controlled by the i/o ram control field mux_div [3:0] (i/o ram 0x2100[7:4]) (see figure 4 ) . the mult iplexer always starts at state 0 and proceeds until the number of sensor channels determined by the mux_div [3:0] field setting have b een converted. the 71m6543 requires a unique ce code that is written for the specific meter configurati on. moreover, each ce code requires specific afe and mux settings in order to function properly. table 1 provides the ce code and settings corresponding to the 1- local / 3 - remote sensor configuration shown in figure 2 . table 2 provides the ce code and settings corresponding to the ct configuration shown in figur e 3 . downloaded from: http:///
71m6543f/71m6543g data sheet v2 15 table 1 . required ce code and settings for 1 - local / 3 - remotes i/o ram mnemonic i/o ram location i/o ram setting comments fir_len[1:0] 210c[2:1] 1 288 cycles adc_div 2200[5] 0 fast pll_fast 2200[4] 1 19.66 mhz mux_div[3:0] 2100[7:4] 6 see note 1 mux0_sel[3:0] 2105[3:0] 0 slot 0 is iadc 0 - iadc1 ( in ) mux1_sel[3:0] 2105[7:4] 1 unused (see note 2) mux2_sel[3:0] 2104[3:0] 1 unused (see note 2) mux3_sel[3:0] 2104[7:4] 8 slot 3 is vadc 8 (v a) mux4_sel[3:0] 2103[3:0] 9 slot 4 is vadc 9 (vb ) mux5_sel[3:0] 2103[7:4] a slot 5 is vadc 10 (v c) mux6_sel[3:0] 2102[3:0] 0 slots not enabled mux7_sel[3:0] 2102[7:4] 0 mux8_sel[3:0] 2101[3:0] 0 mux9_sel[3:0] 2101[7:4] 0 mux10_sel[3:0] 2100[3:0] 0 rmt 2 _e 2709[3] 1 enable remote i adc2 -i adc3 (i a) rmt4 _e 2709[4] 1 enable remote iadc4 -i adc5 (i b) rmt6 _e 2709[5] 1 enable remote i adc6 -i adc7 (i c) diff0 _e 210c[4] 1 differential iadc0 - iadc1 (in) diff2 _e 210c[5] 0 see note 3 diff4 _e 210c[6] 0 see note 3 diff6 _e 210c[7] 0 see note 3 pre_e 2704[5] 1 ia dc0 - ia dc1 gain = 8 equ[2:0] 2106[7:5] 5 ia*va + ib*vb + ic*vc ce code s (see note 4) ce43b016603 (use with 71m6603) ce43b016103 (use with 71m6103) ce43b016113 (use with 71m6113) ce43b016203 (use with 71m6203) equation(s) 5 current sensor type 1 local shunt and 3 remote shunts applicable figure s figure 2 , figure 4 and figure 31 notes: 1. mux_div[3:0] must be set to 0 while writing the other ram locations in this table. 2. each unused slot must be assigned to a valid (0 to a), but unused adc handle . 3. this channel is remote (71m6xx3), hence diffx_e is irrelevant . 4. must use the ce code that corresponds to the specific 71m6xx3 device used . maxim updates the ce code periodically. c ontact your local maxim representative to obtain the latest ce code and the associated settings. downloaded from: http:///
71m6543f/71m6543g data sheet 16 v2 table 2 . required ce code and settings for ct sensors i/o ram mnemonic i/o ram location i/o ram setting (hex) comments fir_len[1:0] 210c[2:1] 1 288 cycles adc_div 2200[5] 0 fast pll_fast 2200[4] 1 19.66 mhz mux_div[3:0] 2100[7:4] 7 see note 1 mux0_sel[3:0] 2105[3:0] 2 slot 0 is iadc 2 - iadc3 (i a) mux1_sel[3:0] 2105[7:4] 8 slot 1 is vadc 8 (v a) mux2_sel[3:0] 2104[3:0] 4 slot 2 is iadc 4 - iadc5 (ib ) mux3_sel[3:0] 2104[7:4] 9 slot 3 is vadc 9 (v b) mux4_sel[3:0] 2103[3:0] 6 slot 4 is iadc 6 - iadc7 (ic ) mux5_sel[3:0] 2103[7:4] a slot 5 is vadc 10 (v c) mux6_sel[3:0] 2102[3:0] 0 slot 6 is iadc0 - iadc1 ( in C see note 2 ) mux7_sel[3:0] 2102[7:4] 0 slots not enabled mux8_sel[3:0] 2101[3:0] 0 mux9_sel[3:0] 2101[7:4] 0 mux10_sel[3:0] 2100[3:0] 0 rmt2 _e 2709[3] 0 local sensor iadc2 - iadc3 rmt4 _e 2709[4] 0 local sensor iadc4 - iadc5 rmt6 _e 2709[5] 0 local sensor iadc6 - iadc7 diff0 _e 210c[4] 1 differential iadc0 - iadc1 diff2 _e 210c[5] 1 differential iadc2 - iadc3 diff4 _e 210c[6] 1 differential iadc4 - iadc5 diff6 _e 210c[7] 1 differential iadc6 - iadc7 pre_e 2704[5] 0 ia dc0 - iadc1 gain = 1 equ[2:0] 2106[7:5] 5 ia*va + ib*vb + ic*vc ce code ce43a02 equation(s) 5 current sensor type 4 current transformers (cts) applicable figure s figure 3 , figure 4 and figure 32 notes: 1. mux_div[3:0] must be set to 0 while writing the other ram locations in this table. 2. in is the optional neutral current . maxim updates the ce code periodically. c ontact your local maxim representative to obtain the latest ce code and the associated settings. downloaded from: http:///
71m6543f/71m6543g data sheet v2 17 using settings for the i/o ram mnemonics listed in table 1 and table 2 that do not match those required by the corresponding ce code being used may result in undesirable side effects and must not be selected by the mpu. consult your local maxim representative to obtain the correct ce code and afe / mux settings corresponding to the application. for a polyphase configuration with neutral current sensing using shunt resistor current sensors and the 71m6xx3 isolated sensors , as shown in figure 2 , the iadc0 - iadc1 input must be configured as a differential input, to be connected to a local shunt (see figure 30 for the shunt connection details). the local shunt connected to the ia dc0 - iadc1 input is used to sense the n eutral current. the voltage sensors (va dc8 , v adc9 and v adc10 ) are also directly connected to the 71m6543 (see figure 27 for the connection details) and are also routed though the multiplexer, as seen in figure 2 . meanwhile, the iadc2 - iadc3 , i adc4 - iadc5 and i adc6 - iadc7 current inputs are configured as remote sensor digital inter faces and the corresponding samples are not routed through the multiplexer. for thi s configuration, the multiplexer sequence is as shown in figure 4 . for a polyphase configuration with optional neutral current sensing using current transformer (cts) sensors, as shown in figure 3 , all four current sensor inputs must be configured as a different ial input s , to be connected to their corresponding cts (see figure 29 for the differential ct connection details). the i adc0 - iadc1 current sensor input is optionally used to sense the neutral current for anti - tampering purposes . the voltage sensors (va dc8 , v adc9 and v adc10 ) are directly connected to the 71m6543 (see figure 27 for the voltage sensor connection details) . no 71m6xx3 isolated sensors are used in this configuration and all sensors are routed though the multiplexer, as seen in fig ure 3 . for this configuration, the multiplexer sequence is as shown in figure 5 . the multiplexer sequence shown in figure 4 corresponds to the configuration shown in figure 2 . t he frame duration is 13 ck32 cycles (where ck32 = 32 , 768 hz), therefore, the resulting sample rate is 32 , 768 hz / 13 = 2 , 520.6 hz. note that figure 4 only shows the currents that pass through the 71m6543 multiplexer, and does not show the currents that are copied directly into ce ra m from the remote sensors (see figure 2 ), which are sampled during the second half of the multiplexer frame. the two unused conversion slots shown are necessary to produc e the desired 2,520.6 hz sample rate. ck32 mux state 0 1 2 3 4 5 mux_div[3:0] = 6 conversions settle multiplexer frame s cross mux_sync s in unused unused va vb vc figure 4 : states in a multiplexer frame ( mux_div [3:0] = 6) the multiplexer sequence shown in figure 5 corresponds to the ct configuration shown in figure 3 . since in this case all current sensors are locally connected to the 71m6543, all currents are routed through the multiplexer, as seen in figure 3 . for this multiplexer sequence, the frame duration is 15 ck32 cycles (where ck32 = 32,768 hz), therefore, the resulting sample rate is 32,768 hz / 15 = 2,184.5 hz. ck32 mux state 0 1 2 3 4 5 mux_div[3:0] = 7 conversions settle multiplexer frame s cross mux_sync s 6 ia va ib vb ic vc in figure 5 : states in a multiplexer frame ( mux_div [3:0] = 7) downloaded from: http:///
71m6543f/71m6543g data sheet 18 v2 mult iplexer ad vance, fir initiation and chopping of the adc reference voltage (using the internal cross signal, see 2.2.7 voltage references ) are controlled by the inter nal mux_ctrl circuit . additionally, mux_ctrl launches each pass of the ce through its code. mux_ctrl is clocked by ck32, the 32768 hz clock from the pll block. the behavior of the mux_ctrl circuit is governed by : ? chop_e[1:0] ( i/o ram 0x2106[3:2] ) ? mux_div[3:0] ( i/o ram 0x2100[7:4] ) ? fir_len [1:0] ( i/o ram 0x210c[2:1 ] ) ? adc_div ( i/o ram 0x2200[5] ) the duration of each multiplexer state depends on the number of adc samples processed by the fir as determined by the fir_len [1:0] (i/o ram 0x210c[2:1] control field . each multiplexer state start s on the rising edge of ck32, the 32 - khz clock. it is required that mux_div [3:0] (i/o ram 0x2100 [7:4 ]) be set to zero while changing the adc configuration to minimize system transients . after all configuration bits are set, mux_div [3:0] should be set to the required value. the duration of each time slot in ck32 cycles depends on fir_len [1:0], adc_div and pll_fast : time_slot_duration = (3 - 2* pll_fast )* ( fir_len [1:0] +1 ) * ( adc_div +1) th e duration of a multiplexer frame in ck32 cycles is: mux_frame_d uration = 3- 2* pll_fast + time_slot_duration * mux_div [3:0] the duration of a multiplexer frame i n ck_fir cycles is: mux frame duration (ck_fir cycles) = [3 - 2* pll_fast + time_slot_duration * mux_div ] * (48+ pll_fast *102) the adc conversion sequence is programmable through the mux n _sel control fields ( i/o ram 0x2100 to 0x2105 ). as stated above, there are up to eleven adc time slots in the 71m654 3 , as set by mux_div[3:0] ( i/o ram 0x210 0[7:4] ) . in the expression mux n _sel [3:0] = x , n refers to the multiplexer frame time slot number and x refers to the desired adc input number or adc handle (i.e., iadc0 to vadc10 , or simply 0 to 10 decimal). thus, there are a total of 11 valid a dc handles in the 71m654 3 devices. for example, if mux 0 _sel [3:0] = 0 , then iadc0 , corresponding to the sample from the iadc0 - iadc1 input (configured as a differential input), is positioned in the multiplexer frame during time slot 0 . see table 1 and table 2 for the appropriate mux n _sel[3:0] settings and other settings applicable to a particular meter configuration and ce code. note that when the remote sensor interface is enabled, the samples corresponding to the remote sensor current s do not pass through the 71m6543 multiplexer. the sampling of the remote current sensors occurs in the second half of the multiplexer frame. the va, vb and v c voltages are assigned the last three slots in the frame. with this slot assignment for va, vb and vc, the sampling of the corresponding remote sensor current s bears a precise timing relationship to their corresponding phase voltages, and delay compensation is accurately performed (see 2.2.3 delay compensation on page 19 ). a lso when using remote sensors, it is necessary to introduce unused slots to realiz e the number of slots specifi ed by the mux_div[3:0] ( i/o ram 0x2100[7:4] ) field setting (see figure 4 and figure 5 ). t he mux n _sel[3:0] contr ol fields for the se unused (dummy) slots must be written with a valid adc handle (i.e., 0 to 10 decimal) that is not otherwise being used. in this manner, the unused adc han dle , is used as a dummy place holder in the multiplexer frame, and the correct duration multiplexer frame sequence is generated and also the desired sample rate. the resulting sample data stored in the ce ram location corresponding to the dummy adc handle is ignored by the ce code. meanwhile, the digital isolation interface takes care of automatically storing the samples for the remote current sensors in the appropriate ce ram locations. downloaded from: http:///
71m6543f/71m6543g data sheet v2 19 delay compensation and other functions in the ce code require the settings for m ux_div[3:0], m ux n _sel [3:0], rmt_e, fir_len[1:0], adc_div and pll_ fast to be fixed for a given ce code. refer to table 1 and table 2 for the settings that are applicable to the 71m654 3. table 3 summarizes the i/o ram registers used for configuring the multiplexer, signals pins, and adc. all listed registers are 0 after reset and wake from battery modes, and are readable and writabl e. table 3: multiplexer and adc configuration bits name location description mux0_sel[3:0] 2105[3:0] selects the adc input converted during time slot 0. mux1_sel[3:0] 2105[7:4] selects the adc input converted during time slot 1. mux2_sel[3:0] 2104[3:0] selects the adc input converted during time slot 2. mux3_sel[3:0] 2104[7:4] selects the adc input converted during time slot 3. mux4_sel[3:0] 2103[3:0] selects the adc input converted during time slot 4. mux5_sel[3:0] 2103[7:4] selects the adc input converted during time slot 5. mux6_sel[3:0] 2102[3:0] selects the adc input converted during time slot 6. mux7_sel[3:0] 2102[7:0] selects the adc input converted during time slot 7. mux8_sel[3:0] 2101[3:0] selects the adc input converted during time slot 8. mux9_sel[3:0] 2101[7:0] selects the adc input converted during time slot 9. mux10_sel[3:0] 2100[3:0] selects the adc input converted during time slot 10. adc_div 2200[5] controls the rate of the adc and fir clocks. mux_div[3:0] 2100[7:4] the number of adc time slots in each multiplexer frame (maximum = 11). pll_fast 2200[4] controls the speed of the pll and mck. fir_len[1:0] 210c[2:1] determines the number of adc cycles in the adc decimation fir fi lter. diff0 _e 210c[4] enables the differential configuration for analog input pins iadc0 - iadc1 . diff2 _e 210c[5] enables the differential configuration for analog input pins iadc2 - iadc3 . diff4 _e 210c[6] enables the differential configuration for analog input pins iadc4 - iadc5 . diff6 _e 210c[7] enables the differential configuration for analog input pins iadc6 - iadc7 . rmt2 _e 2709[3] enables the remote sensor interface transforming pins iadc2 - iadc3 into a digital interface for communications with a 71m6x x3 sensor. rmt4 _e 2709[4] enables the remote sensor interface transforming pins iadc4 - iadc5 into a digital interface for communications with a 71m6xx3 sensor. rmt6 _e 2709[5] enables the remote sensor interface transforming pins iadc6 - iadc7 into a digital interface for communications with a 71m6xx3 sensor. pre_e 2704[5] enables the 8x pre - amplifier. refer to table 70 starting on page 102 for more complete details about these i/o ram locations. 2.2.3 delay compensation when measuring the energy of a phase (i.e., wh and varh) in a service, the vol tage and current for that phase must be sampled at the same instant. otherwise, the phase difference, , introduces errors. o delay o delay f t t t 360 360 ? ? = ? = where f is the frequency of the input signal , t = 1/f and t delay is the sampling delay between current and voltage . tradition ally, sampling is accomplished by using two a/d converters per phase (one for voltage and the other one for current) controlled to sample simultaneously. maxims single converter technology, however, exploits the 32 - bit signal processing capability of its ce to implement constant delay all - pass filters. the all - pass filter corrects for the conversion time difference between the voltage and the corresponding current samples that are obtained with a single multiplexed a/d co nverter. the constant delay all - pass filter provides a broad - band delay 360 o - , which is precisely matched to the difference in sample time between the voltage and the current of a given phase. this digital filter does not affect the amplitude of the signal, but provides a precisely controlled phas e response. downloaded from: http:///
71m6543f/71m6543g data sheet 20 v2 the recommended adc multiplexer sequence samples the current first, immediately followed by sampling of the corresponding phase voltage, thus the voltage is delayed by a p hase angle relative to the current. the delay compensation implemented in the ce aligns the voltage samples with their corresponding current samples by first delaying the current samples by one full sample interval (i.e., 360 o ), then routing the voltage samples through the all - pass filter, thus delaying the voltage samples by 3 60 o - , resulting in the residual phase error between the current and its corresponding voltage of C . the residual phase error is negligible, and is typically less than 1.5 m illi - degrees at 100hz, thus it does not contribute to errors in the energy measurements. when using remote sensors, the ce performs the same delay compensation descri bed above to align each voltage sample with its corresponding current sample. even though the remote current samples do not pass through the 71m6543 multiplexer, their timing relationship to their c orresponding voltages is fixed and precisely known, provided that the muxn_sel[3:0] slot assignment fields are programmed as shown in table 1 . note that these slot assignments result in va, vb and vc occupying mul tiplexer slots 3, 4 and 5, respectively (see figure 4 ). 2.2.4 adc pre -a mp lifier the adc pre - amp lifier is a low - noise differential amplifier with a fixed gain of 8 available only on the iadc0 - iadc1 sensor input pins . a gain of 8 is enabled by setting pre_e = 1 ( i/o ram 0x2704[5] ). when disabled, the supply current of the pre - amplifier is <10 na and the gain is unity . with proper settings of the pre_e and diff0 _e ( i/o ram 0x210c[4] ) bits, the pre - amplifier can be used whether diffe rential mode is selected or not. for best performance, the differential mode is recomme nded. in order to save power, the bias current of the pre - amplifier and adc is adjusted according to the adc_div control bit ( i/o ram 0x2 200 [5] ). 2.2.5 a/d converter (adc) a single 2 nd order sigma - delta a/d converter digitizes the voltage and current inputs to the device. the resolution of the adc, including the sign bit , is 21 bits ( fir_len [1:0] = 01 , i/o ram 0x210c[ 2: 1] ), or 22 bits ( fir_len [1:0] = 10 ). the adc is clocked by ckadc. initiation of each adc conversion is controlled by the internal mux_ctrl circuit as described earlier . at the end of each adc conversion, the fir filter output data is stored into the ce ram locat ion determined by the multiplexer selection . 2.2.6 fir filter the finite impulse response filter is an integral part of the adc and it is optimized for use with the multi plexer. the purpose of the fir filter is to decimate the adc output to the desir ed resolution. at the end of each adc conversion, the output data is stored into the fixed ce ram location determined by the multiplex er selection stored in the muxn_sel[3:0] fields . fir data is stored after being shifted left by 9 bits. 2.2.7 voltage references a bandgap circuit provides the reference voltage to the adc. the amplifier within the reference is chopper stabilized, i.e. , the chopper circuit can be enabled or disabled by the mpu using the i/o ram control field chop_e [1:0] (i/o ram 0x2106[3:2]) . the two bits in the chop_e [1:0] field enable the mpu to operate the chopper circuit in regula r or inverted operation, or in toggling mode s (recommended) . when the chopper circuit is toggled in between mul tiplexer cycles, dc offsets on vref are automatically be averaged out, therefore the chopper circuit should always be configured for one of the toggli ng modes. since the vref band - gap amplifier is chopper - stabilized, the dc offset voltage, which is the most significant long - term drift mechanism in the voltage references (vref), is automatically removed by the chopper circuit. both the 71m6543 and the 71m6xx3 feature chopper circuits for their respective vref voltage reference. the general topology of a chopped amplifier is shown in figure 6 . the cross signal is an internal on - chip signal and is not accessible on any pin or register. downloaded from: http:///
71m6543f/71m6543g data sheet v2 21 figure 6 : general topology of a chopped amplifier it is assumed that an offset voltage voff appears at the positive amplifier i nput. with all switches, as controlled by cross (an internal signal), in the a position, the output voltage is : voutp C voutn = g (vinp + voff C vinn) = g (vinp C vinn) + g voff with all switches set to the b position by applying the inverted cross signal, the output voltage is: voutn C voutp = g (vinn C vinp + voff) = g (vinn C vinp) + g voff, or voutp C voutn = g (vinp C vinn) - g voff thus, when cross is toggled, e.g., after each multiplexer cycle, the of fset alternately appears on the output as positive and negative, which results in the offset effectively being eliminated, regardless of its polarity or magnitude. when cross is high, the connection of the amplifier input devices is reversed. this preserves the overall polarity of that amplifier gain; it inverts its input offset. by alternate ly reversing the connection, the amplifiers offset is averaged to zero. this removes the most significant long - term drift mechanism in the voltage reference. the chop_e [1:0] ( i/o ram 0x2 106 [3:2] ) control field control s the behavior of cross. on the first ck32 rising edge after the last multiplexer state of its sequence, the multiplexer wai t s one additional ck32 cycle before beginning a new frame. at the beginning of this cycle, the value of cross is updated according to the chop_e [1:0] field . the extra ck32 cycle allows time for the chopped vref to settle. during this cycle, muxsync is held high. the leading edge of muxsync initiates a pass through the ce program sequence . chop_e [1:0] has four states: positive, reverse, and two toggle states. in the positive state, chop_e [1:0] = 01, cross is held low. in the reverse state, chop_e [1:0] = 10, cross is held high. the two automatic toggling states are selected by setting chop_e=11 or chop_e=00 . figure 7 : cross signal with chop _e = 00 figure 7 shows cross over two accumulation intervals when chop_e [1:0] = 00: at the end of the first in ter val, cross is high, at the end of the second interval, cross is low . operation with chop_e [1:0] = 00 does not require control of the chopping mechanism by the mpu. in the second toggle state, chop_e [1:0] = 11, cross does not toggle at the end of the last multiplexer cycle in an accumulati on interval . g - + v inp v outp v outn v inn cross ab ab a b a b downloaded from: http:///
71m6543f/71m6543g data sheet 8 22 v2 2.2.8 71m6xx3 isolated sensor interface 2.2.8.1 general description non - isolating sensors, such as shunt resistors, can be connected to the inputs of the 71m6543 via a combination of a pulse transformer and a 71m6xx3 ic (a top - level block diagram of this sensor interface is shown in figure 31 ). the 71m6xx3 receives power directly from the 71m6543 via a pulse trans former and does not require a dedicated power supply circu it. the 71m6xx3 establishes 2 - way communication wit h the 71m6543, supplying current samples and auxiliary information such as sensor t emperature via a serial data stream. up to three 71m6xx3 isolated sensor s can be supported by the 71m654 3. when a remote sensor interface is enabled, the two analog current inputs become re - configured a s a digital remote sensor interface. for example, when control bit rmt2 _e = 1, the i adc2 -i adc3 analog pins are re - configured as the digital interfac e pins to the remote sensor . each 71m6x x3 isolated sensor consists of the following building blocks: ? power supply that derives power from pulses received from the 71m654 3 ? bi - directional digital communications interface ? shunt signal pre - amplifier ? 22 - bit 2nd order sigma - delta adc converter with pre cision bandgap reference (chopping amplifier) ? temperature sensor (for digitally compensating vref) ? fuse system containing part - specific information during an ordinary mu ltiple x er cycle, the 71m654 3 internally determines which other channels are enabled wit h mux_div[3:0] (i/o ram 0x2100[7:4]) . at the same time, it decimate s the modulator output from the 71m6x x3 isolated s ensors. each result is written to ce ram during one of its ce access time slots. 2.2.8.2 communication between 71m654 3 and 71m6x x3 isolated sensor the adc of the 71m6x x3 derives its timing from the power pulses generated by the 71m654 3 and as a result, operates its adc slaved to the frequency of the power pulses. the generation of power pulses, as well as the communication protocol between the 71m654 3 and 71m6x x3 isolated sensor, is automatic and transparent to the user. details are not covered in this data sheet. 2.2.8.3 control of the 71m6x x3 isolated sensor the 71m6543 can read or write certain types of information from each 71m6xx3 remote sensor. the data to be read is selected by a combination of th e rcmd[4:0] and tmuxrn[2:0] . to perform a read transaction from one of the 71m6xx3 devices, the mpu first wri tes the tmuxrn [2:0 ] field (where n = 2, 4, 6, located at i/o ram 0x270a[2:0] , 0x270a[ 6:4] and 0x270 9 [2:0] , respectively ) . next, the mpu writes rcmd[4:0 ] ( sfr 0xfc[4:0] ) with the desired command and phase selection . when the rcmd[4:2] bits have cleared to zero, the transaction has been completed and the requested data is available in rmt _rd[15: 0] ( i /o ram 0x2602[7:0] is the msb and 0x2603[7:0] is the lsb) . the read parity error bit, perr _r d (sfr 0xfc[6]) is also updated during the transaction . if the mpu writes to rcmd[4:0] before a previously initiated read transaction is completed , the command is ig nored. therefore, the mpu must wait for rcmd[4:2] =0 before proceeding to issue the next remote sensor read command. if the ce is running ( ce_e =1), the mpu must write rcmd[4:0] immediately after a ce_busy rising edge. rcmd[4:0] must be written before the next rising edge of mux_sync. failure to do this can cause incorrect data to be read. the rcmd[4:0] field is divided into two sub - fields, command =rcmd[4:2] and phase=rcmd[1:0] , as shown in table 4 . . downloaded from: http:///
8 71m6543f/71m6543g data sheet v2 23 table 4 . rcmd[4:0] bits command rcmd[4:2] phase selector rcmd[1:0] associated tmuxrn control field 000 invalid 00 invalid --- 001 command 1 01 iadc 2 - iadc3 tmuxr 2 [2:0] 010 command 2 10 i adc 4 - iadc 5 tmuxr 4 [2:0] 011 reserved 11 iadc 6 - iadc 7 tmuxr 6 [2:0] 100 reserved 101 invalid 110 reserved 111 reserved notes: 1. only two codes of rcmd[4:2 ] ( sfr 0x fc[4:2] ) are relevant for normal operation. these are rcmd[4:2 ] = 001 and 010. codes 000 and 101 are invalid and will be ignored if used. the remaining codes are re served and must not be used. 2. for the rcmd [1 :0 ] control field, codes 01, 10 and 11 are valid and 00 is invalid and must not be used. 3. the specific phase (a, b or c) associated with each tmuxrn[2:0] field, is de termined by how the iadcn input pins are connected in the meter design. table 5 shows the allowable combinations of values in rcmd[4:2 ] a nd tmuxrn[2:0 ] , and the corresponding data type and format s ent back by the 71m6xx3 remote s en sor and how the data is stored in rmt_rd[15:8] and rmt_rd[7:0] . the mpu selects which of the three phases is read by asserting the proper code in the rcmd[1:0] field, as shown in table 4 . . table 5: remote interface read commands rcmd[4:2] tmuxrn[2:0] read operation rmt_rd [15:8] rmt_rd [7:0] 001 00x trimt[7:0] ( trim fuse for all 71m6xx3) trimt[7]=rmt_rd[8] trimt[6:0]=rmt_rd[7:1] 001 11x trimbgb[ 7 :0] and trimbg d[7 :0] ( additional trim fuses for 71m611 3 and 71m6203 only ) trimbg b[7 :0] trimbg d[7 :0] 010 00x stemp[10:0] (sensed 71m6xx3 temperature) stemp[10:8]=rmt_rd[ 10 :8] (rmt_rd[15: 11 ] are sign extended) stemp[7:0] 010 01x vsense[ 7 :0] (sensed 71m6xx3 supply voltage) all zeros vsense[7:0] 010 10x version[7:0] (chip version) version [7 :0] all zeros notes: 1. trimt[7:0] is the vref trim value for all 71m6xx3 devices . note that t he trimt[7:0] 8- bit value is formed by rmt_rd[8] and rmt_rd[7:1] . see the 71m6xxx data sheet for the equations related to trimt[7:0] and the corresponding temperature coefficient . 2. trimbg b[7 :0] and trimbgd [7:0] are trim values used for characterizing the 71m6113 (0.5%) and 71m6203 (0.1%) over temperature. see the 71m6xxx data sheet for the equations related to trimbgb[7:0] and trimbgd[7:0] and the corresponding temperature coefficients. 3. see 2.5.6 71m6xx3 temperature sensor on page 56 . 4. see 2.5.8 71m6xx3 vcc monitor on page 56 . with hardware and trim - related information on each connected 71m6xx3 isolated sensor available to the 71m6543 , the mpu can implement temperature compensation of the energy measurement base d on the individual temperature characteristics of the 71m6xx3 isolated sensors. see 4.5 metrology temperature compensation for details. table 6 shows all i/o ram registers used for control of the external 71m6x x3 isolated sensors. see the 71m6x x3 data sheet for additional details. downloaded from: http:///
71m6543f/71m6543g data sheet 8 24 v2 table 6: i/o ram control bits for isolated sensor name addr ess rst default wake default r/w description rcmd[4:0] sfr fc[4:0] 0 0 r/w when the mpu writes a non - zero value to rcmd , the 71m654 3 issue s a command to the cor - responding isolated sensor selected with rcmd[1:0] . when the command is complete, the 71m654 3 clear s rcmd[4:2]. the command code itself is in rcmd[4:2 ]. perr_rd perr_wr sfr fc[6] sfr fc[5] 0 0 r/w the 71m654 3 set s these bits to indicate that a parity error on the isolated sensor has been de - tected. once set, the bits are re mem bered until they are cleared by the mpu. chopr[1:0] 2709[7:6] 00 00 r/w the chop settings for the is o la te d sensors. 00 C auto chop. change every multiplexer frame. 01 C positive 10 C negative 11 C same as 00 tmuxr2 [2:0] 270 a [2:0] 000 000 r/w the tmux bits for control of the isolated sensor . tmuxr4 [2:0] 270 a[6:4] 000 000 r/w the tmux bits for control of the isolated sensor . tmuxr6 [2:0] 270 9[2 :0] 000 000 r/w the tmux bits for control of the isolated sensor . rmt _rd[15:8] rmt _rd[7:0] 2602[7:0] 2603[7:0] 0 0 r the read buffer for 71m6x x3 read operation s. rfly_dis 210c[3] 0 0 r/w controls how the 71m654 3 drives the 71m6x x3 power pulse. when set, the power pulse is driven high and low. when cleared, it is driven high followed by an open circuit fly - back interval. rmt2 _e 2709[3] 0 0 r/w enables the isolated remote sensor interface and re - configures pins i adc2 - iadc3 as a balanced pair digital remote interface. rmt4 _e 2709[4 ] 0 0 r/w enables the isolated remote sensor interface and re - configures pins i adc4 - iadc5 as a balanced pair digital remote interface . rmt6 _e 2709[5 ] 0 0 r/w enables the isolated remote sensor interface and re - configures pins i adc6 - iadc7 as a balanced pair digital remote interface . refer to table 70 starting on page 102 for more complete details about these i/o ram locations. downloaded from: http:///
71m6543f/71m6543g data sheet v2 25 2.3 digital computation engine (ce) the ce, a dedicated 32 - bit signal processor, performs the precision computations necessary to acc urately measure energy. the ce calculations and processes include: ? multiplication of each current sample with its associated voltage sample to obtain the energ y per sample (when multiplied by the constant sample time). ? frequency - insensitive delay cancellation on all channels (to compensate for the delay bet ween samples caused by the multiplexing scheme). ? 90 phase shifter (for var calculations). ? pulse generatio n. ? monitoring of the input signal frequency (for frequency and phase information). ? monitoring of the input signal amplitude (for sag detection). ? scaling of the processed samples based on calibration coefficients. ? scaling of samples based on temperature compensation information. 2.3.1 ce program memory the ce program resides in flash memory. common access to flash memory by the ce and mpu is con trolled by a memory share circuit. each ce instruction word is two bytes long. allocated flash space for the ce program cannot exceed 4096 16 - bit words (8 kb). the ce program counter begins a pass through the ce code each time multiplexer state 0 begins. the code pass ends when a halt instruction is executed. for proper operation, the code pass must be completed before the multiplexer cyc le ends . the ce program must begin on a 1 kb boundary of the flash address. the i/o ram control field ce_lctn[ 6/ 5 :0] ( i/o ram 0x2109[ 6/ 5: 0] ) on the 71m6543f and ce_lctn[ 6 :0] ( i/o ram 0x2109[6 :0] ) on the 71m6543g defines which 1 kb boundary contains the ce code. thus, the first ce instruction is located at 1024* ce_lctn[ 5 :0] on the 71m6543f and 1024* ce_lctn[6 :0 ] on the 71m6543g. 2.3.2 ce data memory the ce and mpu share data memory (ram). common access to xram by the ce and mpu is controlled by a m emory share circuit. the ce can access up to 3 kb of the 5 kb data ram (xram) , i.e. from ram address 0x0000 to 0x0c00 . the xram can be accessed by the fir filter block, the rtm circuit, t he ce, and the mpu. assigned time slots are reserved for fir and mpu, respectively, to prevent bus contention for xram data access by the ce . the mpu read s and write s the xram shared between the ce and mpu as the primary means of data communication between the two processors. the ce is aided by support hardware to facilitat e implementation of equations, pulse counters, and ac cumulators. this hardware is controlled through i/o ram field equ[2:0] (equation assist, i/o ram 0x2106[7:5] ), bit dio_pv (i/o ram 0x2457[6]), bit dio_pw (pulse count assist , i/o ram 0x2457[7] ), and sum_ samps [12:0] (accumulation assist , i/o ram 0x2107[4:0] and 0x2108[7:0] ). the integration time for each energy output, when using standard ce code, is sum_samps[12:0] /218 4 .53 (with mux_div[3:0] = 7 , i/o ram 0x2100[7:4] ). ce hardware issues the xfer_busy interrupt when the accumulation is complete. 2.3.3 ce communication with the mpu the ce outputs six signals to the mpu: ce_busy, xfer_busy, xpulse, ypulse , wpulse and vpulse . these are connected to the mpu interrupt service. ce_busy indicates that the ce is act ively processing data. this signal occur s once every multiplexe r frame. xfer_busy indicates that the ce is updating to the o ut put region of the ce ram, which occur s whenever an accumulation cycle has been completed. both, ce_busy and xfer_busy are cleared when the ce executes a halt instruction. xpulse and ypulse can be configured to interrupt the mpu and indicate zero crossings of the mains voltage, sag failures , or other significant events. additionally, these signals can be connected directly to dio pin s to provide di rect outputs f r om the ce. interrupts associated with these signals always occur on the leading edge. downloaded from: http:///
71m6543f/71m6543g data sheet 26 v2 2.3.4 meter equations the 71m6543 provide s hardware assistance to the ce in order to support various meter equations. this assistance is controlled through i/o ram field equ[2:0] (equation assist , i/o ram 0x2106[7:5] ) . the compute engine (ce) firmware configurations can implement the equations listed in table 7 . equ[2:0] specifies the equation to be used based on the meter configuration and on t he number of phases used for metering. table 7 : inputs selected in multiplexer cycles equ[2:0] * description wh and varh formula recommended multiplexer sequence element 0 element 1 element 2 2 2- element, 3 - w, 3 delta va ia vb ib n/a ia va ib vb 3 2- element, 4 - w, 3 delta va(ia - ib)/2 vc ic n/a ia va ib vb ic vc 4 2- element, 4 - w, 3 wye va(ia - ib)/2 vb(ic - ib)/2 n/a ia va ib vb ic vc 5 3- element, 4 - w, 3 wye va ia vb ib vc ic ia va ib vb ic vc (id) note: * only equ[2:0] = 5 is supported by the currently available ce code versions for the 71m6 543. contact your local maxim representative for ce codes that support equations 2, 3 , and 4. 2.3.5 real - time monitor (rtm) the ce contains a real - time monitor (rtm), which can be programmed to monitor four selectable x ram locations at full sample rate. the data from the four monitored locations are serially output to the tmuxout pin via the digital output multiplexer at the beginning of each ce code pass. the rtm can be enabled and disabled with rtm_e (i/o ram 0x2106[1]) . the rtm output clock is available on the tmux2out pin . each rtm word is clocked out in 35 cycles and contains a leading flag bit. see figure 8 for the rtm output format. rtm is low when not in use. figure 8 : rtm timing 2.3.6 pulse generator s the 71m6543 provide s fou r pulse generators, vpulse , wpulse, xpulse and ypulse . the xpulse and ypulse generators are used by standard ce code to output ce status indicators, for example the status of the sag detection , to dio pins. all pulses can be configured to generate interrupts to the mpu. the polarity of the pulses may be inverted with pls_inv (i/o ram 0x210c[0]) . when this bit is set, the pulses are active high, rather than the more usual active low. pls_inv inverts all the pulse outputs. the function of each pulse generator is determined by the ce code and the mpu code must configure the corresponding pulse outputs in agreement with the ce code. for example, standard ce code produ ces a mains zero - crossing pulse on xpulse and a sag pulse on ypulse. cktest rtm flag rtm data0 (32 bits) lsb sign lsb sign rtm data1 (32 bits) lsb lsb sign sign rtm data2 (32 bits) rtm data3 (32 bits) 0 1 30 31 0 1 30 31 0 1 30 31 0 1 30 31 flag flag flag mux_state s mux_sync ck32 downloaded from: http:///
71m6543f/71m6543g data sheet v2 27 a common use of the zero - crossing pulses is to generate interrupts in order to drive real - time clock software in places where the mains frequency is sufficiently accurate to do so and also to adjust for crystal aging. a common use for the sag pulse is to generate an interrupt that al erts the mpu when mains power is about to fail, so that the mpu code can store accumulated energy and ot her data to eeprom before the v3p3sys supply voltage ac tually drops. 2.3.6.1 xpulse and ypulse pulses generated by the ce may be exported to the xpulse and ypulse pul se output pins. pins segdio6 and segdio7 are used for these pulses, respectively. generally, the xpulse and ypulse outputs can be updated once on each pass of the ce code . see 5.3 ce interface description on page 116 for details. 2.3.6.2 vpulse and wpulse referring to figure 9 , d uring each ce code pass the hardware stores exporte d wpul se and v pulse sign bits in an 8 - bit fifo and outputs them at a specified interval. this permits the ce code to calculate the vpulse and wpulse outputs at the beginning of its code pass and to rely on hardware to spread them over the multiplexer frame. as seen in figure 9 , t he fifo is reset at the beginning of each multiplexer frame. as also seen in fig ure 9 , t he i/o ram register pls_interval [7:0] (i/o ram 0x210b [7:0] ) controls the delay to the first pulse update and the interval between subsequent updates. the lsb of the pls_interval [7:0] register is equivalent to 4 ck_fir cycles (ck_fir is typically 4.9152mhz if pll_fast =1 and adc_div =0, but other ck_fir frequencies are possible; see the adc_div definition in table 70 .) if pls_interval[7:0] =0 , the fifo is deactivated and the pulse output s are updated immediately. the mux frame duration in units of ck_fir clock cycles is given by : if pll_fast =1: mux frame duration in ck_fir cycles = [1 + ( fir_len +1) * ( adc_div +1) * ( mux_div )] * [150 / ( adc_div +1)] if pll_fast =0: mux frame duration in ck_fir cycles = [ 3 + 3*( fir_len +1) * ( adc_div +1) * ( mux_div )] * [48 / ( adc_div +1)] pls_interval[7:0] in units of ck_fir cloc k cycles is calculated by: pls_interval [7:0] = floor ( mux frame duration in ck_fir cycles / ce pulse updates per mux frame / 4 ) since the fifo resets at the beginning of each multiplexer frame, the user must specify pls_interva l[7:0] so that all of the p ossible pulse updates occurring in one ce execution are output before the multiplexer frame completes. for instance, the 71m6543 c e code outputs six updates per multiplexer interval, and if the multiplexer interval is 1950 ck_fir clock cycles long, the ideal value for the interval is 1950/6 /4 = 81.25 . however, i f pls_interval [7:0] = 82 , the six th output occur s too late and would be lost. in this case, the proper value for pls_interval [7:0] is 81 (i.e., round down the result) . since one lsb of pls_interval[7:0] is equal to 4 ck_fir clock cycles, the pulse time interval t i in units of ck_fir clock cycles is: t i = 4* pls_interval[7:0] if the fifo is enabled (i.e., pls_interval[7:0] 0), h ardware also provides a maximum pulse width feature in control register pls_max width[7:0] (i/o ram 0x210a) . by default, wpulse and vpulse are negative pulses (i.e., low level pulses, designed to sink current through an led). pls_maxwidth[7:0] determines the maximum negative pulse width t max in units of ck_fir clock cycles based on the pulse interval t i according to the formula: t max = (2 * pls_maxwidth [7:0] + 1) * t i if pls_maxwidth = 255 or pls_interval =0, no pulse width checking is performed, and the pulses default to 50% duty cycle. the polarity of t he pulses may be inverted with the control bit pls_inv ( i/o ram 0x210c[0] ). when pls_inv is set, the pulses are active high. the default value for pls_inv is zero, which selects active low pulses. downloaded from: http:///
71m6543f/71m6543g data sheet 28 v2 the wpulse and v pulse pulse generator outputs are available on pins segdio0/wpulse and segdio1/vpulse , respectively (pins 45 and 44) . the pulses can also be output on opt_tx pin 53 (see opt_txe[1:0] , i/o ram 0x2456[3:2] for details). figure 9 . pulse generator fifo timing 2.3.7 ce functional overview the adc processes one sample per channel per multiplexer cycle. figure 10 shows the timing of the samples taken during one multiplexer cycle with mux_div[3:0] = 7 (i/o ram 0x2100[ 7:4]) . the number of samples processed during one accumulation cycle is controlled by the i/o ram register sum_samps[12:0] ( 0x2 1 07[4 :0] and 0x2108[7:0] ). the integration time for each energy output is : sum_samps[12:0] / 2184 .53 , w here 2184 .53 is the sample rate in hz for example, sum_samps[12:0] = 2184 establish es 2184 multiplexer cycles per accumulation cycle or 2184/2184.53 = 0.9998 seconds . after an accumulation cycle is completed, the xfer_busy interrupt signals to the mpu that accumulated data are available. the slight difference between the nominal length of the accumulation interval (1000 ms) and the actual length of 999.8 ms (0.025%) is accounted for in the ce code and is of no practical consequence. ck32 mux_div conversions ( mux_div =6 is shown) settle adc mux frame mux_sync 150 wpulse s 0 s 1 s 2 s 3 s 4 s 5 ce code rst w_fifo s 0 s 1 s 2 s 3 s 4 s 5 s 0 s 1 s 2 s 3 s 4 s 5 4* pls_interval 2. if wpulse is low longer than ( 2 *pls_maxwidth+1) updates , wpulse will be raised until the next low - going pulse begins. 3. only the wpulse circuit is shown. the varpulse circuit beh aves identically. 4. all dimensions are in ck_fir cycles (4.92mhz). 5. if pls_interval =0, fifo does not perform delay. 4* pls_interval 4* pls_interval 4* pls_interval 4* pls_interval 4* pls_interval 1. this example shows how the fifo distributes 6 pulse generator updates over one mux frame. downloaded from: http:///
71m6543f/71m6543g data sheet v2 29 figure 10 : samples from multiplexer cycle (frame ) the end of each multiplexer cycle is signaled to the mpu by the ce_bus y interrupt. at th e end of each multiplexer cycle , status information, such as sag data and the digitized input signal, i s available to the mpu. figure 11 : accumulation interval figure 11 shows the accumulation interval resulting fro m sum_samps[12:0] = 1 819 (i/o ram 0x2107[4:0] and 0x2108[7:0] ) , consisting of 1 819 sam ples of 45 7 .8 s each, followed by the xfer_busy interrupt. the sampling in this example is applied to a 50 hz signal. there is no correlation between the line signal frequency and the choice of sum _samps [12:0] . furthermore, sampling does not have to start when the line voltage crosses the zero line, and the length of the accumulation interval ne ed not be an integer mul tip le of the signal cycles. mux state ck32 (32768 hz) 0 3 1 2 mux_div = 7 conversions settle multiplexer frame (15 x 30.518 s = 457.8 s) s s ia va ib 30.5 s 61.04 s vb 61.04 s ic vc 4 5 6 61.04 s 61.04 s id xfer_busy interrupt to mpu 20ms 833ms downloaded from: http:///
71m6543f/71m6543g data sheet 30 v2 2.4 80515 mpu core the 71m6543 include an 80515 mpu (8 - bit, 8051 - compatible) that processes most instructions in one clock cycle. using a 4.9 mhz clock results in a processing throughput of 4.9 mips. the 80515 architecture eliminates redundant bus states and im plements parallel execution of fetch and execution phases. normally , a machine cycle is aligned with a memory fetch, therefore, most of the 1 - byte instructions are performed in a single machine cycle (mpu clock cycle) . this lea ds to an 8x average performance im prove ment (in terms of mips) over the intel ? 8051 device running at the same clock frequency . table 8 shows the ckmpu frequency as a function of the mck clock (19.6608 mhz) div ided by the mpu clock divider mpu_div[2:0] (i/o ram 0x2200[2:0]) . actual processor clocking speed can be adjusted to the total processing demand of the application (metering calculations, amr management, memory management, lcd driver management and i/o management) using mpu_div[2:0] , as shown in table 8 . table 8 : ckmpu clock frequencies mpu_div [2:0] ckmpu frequency 000 4.9152 mhz 001 2.4576 mhz 010 1.2288 mhz 011 614.4 k hz 100 307.2 khz 101 110 111 typical measurement and metering functions based on the results provided by the internal 32 - bit com pute engine (ce) are available for the mpu as part of the maxim demonstrati o n code, which is provided to help reduce the product design cycle . 2.4.1 memory organization and addressing the 80515 mpu core incorporates the harvard architecture with separate code and data spaces. memory organization in the 80515 is similar to that of the industry standard 8051. there are three memory areas: program memory (flash, shared by mpu and ce), external ram (data ram, shared by the ce and mpu, configuration or i/o ram ), and internal data memory (internal ram). table 9 shows the mem ory map. program memory the 80515 can address up to 64 kb of program memory space ( 0x 00 0 0 to 0xffff ). program memory is read when the mpu fetches instructions or performs a movc operation. after reset, the mpu starts program execution from program memory locati on 0x0000. the lower part of the program memory includes reset and interrupt vectors. the interrupt vectors are spaced at 8 - byte in tervals, starting from 0x0003. mpu external data memory (xram) both internal and external memory is physically located on the 71m6543 device . the e x ternal mem ory referred to in this documentation is only external to the 80515 mpu core. 5 kb of ram starting at address 0x0000 is shared by the ce and mpu. the ce norm ally uses the first 1 kb, leaving 4 kb for the mpu. different versions of the ce code use varying amounts. consult the documentation for the specific code version being used for the exact limit. to change the slot assignments established by muxn_sel[3:0] , first set mux_div[3:0] to zero, then change the muxn_sel[3:0] slot assignments, and finally set mux_div[3:0] to the number of active mux frame slots. downloaded from: http:///
71m6543f/71m6543g data sheet v2 31 the 80515 writes into external data memory when the mpu executes a movx @ri,a or movx @dptr,a instruct ion. the mpu reads external data memory by executing a movx a,@ri or movx a,@dptr instruction ( pdata, sfr 0xb f , provides the upper 8 bytes for the movx a,@ri instruction) . internal and external memory map table 9 shows the address, type, use and size of the various memory components. table 9 : memory map address (hex) memory technology memory type name typical usage memory size (bytes) 0000 - ffff flash memory non - volatile program memory mpu program and non - volatile data 64 kb ce program (on 1 kb boundary) 3 kb max. 0000 - 13 ff static ram volatile external ram (xram) shared by ce and mpu 5 kb 2000 - 27 ff static ram volatile configuration ram ( i/o ram ) hardware control 2 kb 2800 - 28 7f static ram non - volatile (battery) configuration ram ( i/o ram ) battery - buffered memory 12 8 0000 - 00ff static ram volatile internal ram part of 80515 core 256 movx addressing there are two types of instructions differing in whether they provide an 8 - bit or 16 - bit indirect address to the external data ram. in the first type, movx a,@ri, the contents of r0 or r1 in the cur rent register bank provide the eight lower - ordered bits of address. the eight high - ordered bits of the address are specified with the pdata sfr. this method allows the user paged access (256 pages of 256 bytes each) to all ranges of the external data ram. in the second type of movx instruction, movx a,@dptr, the data pointer generates a 16 - bit address. this form is faster and more efficient when accessing very large data arrays (up to 64 kb ), since no additional instructions are needed to set up the eight high ordered bits of th e address. it is possible to mix the two movx typ es. this provides the user with four separate data pointers, two with direct access and two with paged access, to the entire 64 kb of external mem ory range. dual data pointer the dual data pointer accelerates the block moves of data. the standard dptr is a 16 - bit register that is used to address external memory or peripherals. in the 80515 core, the standard data pointer is called dptr , the second data pointer is called dptr1 . the data pointer select bit, located in the lsb of the dps register ( dps [0] , sfr 0x92 ) , chooses the active pointer. dptr is selected when dps [0] = 0 and dptr1 is selected when dps [0] = 1. the user switches between pointers by toggling the lsb of the dps register. the values in the data pointers are not affected by the lsb of the dps register. all dptr related instructions use the currently selected dptr for any activity. the second data pointer may not be supported by certain compilers. dptr1 is useful for copy routines, where it can make the inner loop of th e routine two instructions faster compared to the reloading of dptr from registers . any interrupt routine using dptr1 must save and restore dps , dptr and dptr1 , which increases stack usage and slows down interrupt latency. by selecting the evatronics r80515 core in the keil compiler project settings and by using the compiler directive modc2, dual data pointers are enabled in certain library routines. downloaded from: http:///
71m6543f/71m6543g data sheet 32 v2 an alternative data pointer is available in the form of the pdata register ( sfr 0xbf ) , sometimes referred to as usr2 ). it d efines the high byte of a 16 - bit address when reading or writing xdata with the instruction movx a,@ri or movx @ri,a. internal data memory map and access the internal data memory provides 256 bytes (0x00 to 0xff) of data memory . the internal data memory address is always 1 byte wide . table 10 shows the internal data memory map. the special function registers (sfr) occupy the upper 128 bytes . the sfr area of internal data memory is available only by direct addressing . indirect addressing of this area accesses the upper 128 bytes of internal ram . the lower 128 bytes contain working registers and bit addressable memory . the lower 32 bytes form four banks of eight registers (r0 - r7) . two bits on the program memory status word ( psw , sfr 0xd0 ) select which bank is in use . the ne xt 16 bytes form a block of bit addressable memory space at ad dresse s 0x00 - 0x7f . all of the bytes in the lower 128 bytes are accessible through direct or indirect addressing . table 10 : internal data memory map address range direct addressing indirect addressing 0x80 0xff special function registers (sfrs) ram 0x30 0x7f byte addressable area 0x20 0x2f bit addressable area 0x00 0x1f register banks r0r7 2.4.2 special function registers (sfrs) a map of the special function registers is shown in table 11 . only a few addresses in the sfr memory space are occupied, the others are not im plemented. a read access to unimplemented addresses return s undefined data, while a write access ha s no effe ct. sfrs specific to the 71m6543 are shown in bold print on a gray field . the registers at 0x80, 0x88, 0x90, etc., are bit a ddressable, all others are byte addressable. table 11 : special function register map hex/ bin bit addressable byte addressable bin/ hex x000 x001 x010 x011 x100 x101 x110 x111 f8 flag1 vstat remote0 spi1 ff f0 b f7 e8 iflags ef e0 a e7 d8 wdcon df d0 psw d7 c8 t2con cf c0 ircon c7 b8 ien1 ip1 s0relh s1relh pdata bf b0 p3 flshctl fl_bank pgadr b7 a8 ien0 ip0 s0rell af a0 p2 dir2 dir0 a7 98 s0con s0buf ien2 s1con s1buf s1rell eedata eectrl 9f 90 p1 dir1 dps erase 97 88 tcon tmod tl0 tl1 th0 th1 ckcon 8f 80 p0 sp dpl dph dpl1 dph1 pcon 87 downloaded from: http:///
71m6543f/71m6543g data sheet v2 33 2.4.3 generic 80515 special function registers table 12 shows the location, description and reset or power - up value of the generic 80515 sfrs . additional descriptions of the registers can be found at the page numbers listed in the table. table 12 : generic 80515 sfrs - location and reset values name address (hex) reset value (hex) description page (s) p0 0x80 0xff port 0 35 sp 0x81 0x07 stack pointer 34 dpl 0x82 0x00 data pointer low 0 34 dph 0x83 0x00 data pointer high 0 34 dpl1 0x84 0x00 data pointer low 1 34 dph1 0x85 0x00 data pointer high 1 34 pcon 0x87 0x00 power reduction modes, uart speed control 38 tcon 0x88 0x00 timer/counter control 41 tmod 0x89 0x00 timer mode control 39 tl0 0x8a 0x00 timer 0, low byte 38 tl1 0x8b 0x00 timer 1, high byte 38 th0 0x8c 0x00 timer 0, low byte 38 th1 0x8d 0x00 timer 1, high byte 38 ckcon 0x8e 0x01 clock control (stretch=1) 35 p1 0x90 0xff port 1 35 dps 0x92 0x00 data pointer select register 31 s0con 0x98 0x00 serial port 0, control register 37 s0buf 0x99 0x00 serial port 0, data buffer 35 ien2 0x9a 0x00 interrupt enable register 2 41 s1con 0x9b 0x00 serial port 1, control register 37 s1buf 0x9c 0x00 serial port 1, data buffer 35 s1rell 0x9d 0x00 serial port 1, reload register, low byte 35 p2 0xa0 0xff port 2 35 ien0 0xa8 0x00 interrupt enable register 0 40 ip0 0xa9 0x00 interrupt priority register 0 43 s0rell 0xaa 0xd9 serial port 0, reload register, low byte 35 p3 0xb0 0xff port 3 35 ien1 0xb8 0x00 interrupt enable register 1 40 ip1 0xb9 0x00 interrupt priority register 1 43 s0relh 0xba 0x03 serial port 0, reload register, high byte 35 s1relh 0xbb 0x03 serial port 1, reload register, high byte 35 pdata 0xbf 0x00 high address byte for movx@ri - also called usr2 31 ircon 0xc0 0x00 interrupt request control register 41 t2con 0xc8 0x00 polarity for int2 and int3 41 psw 0xd0 0x00 program status word 34 wdcon 0xd8 0x00 baud rate control register (only wdcon[ 7] bit used) 35 a 0xe0 0x00 accumulator 34 b 0xf0 0x00 b register 34 downloaded from: http:///
71m6543f/71m6543g data sheet 34 v2 accumulator ( acc , a , sfr 0x e0 ): acc is the accumulator register . most instructions use the accumulator to hold the operand . the mnemonics for accumulator - specific instructions refer to accumulator as a , not acc . b register ( sfr 0xf0 ) : the b register is used during multiply and divide instructions . it can also be used as a scratch - pad register to hold temporary data. program status word ( psw , sfr 0xd0 ): this register contains various flags and control bits for the selection of the register banks (see table 13 ). table 13 : psw bit functions ( sfr 0xd0 ) psw bit symbol function 7 cv carry flag . 6 ac auxiliary carry flag for bcd operations . 5 f0 general purpose flag 0 available for user. f0 is not to be confused with the f0 flag in the cestatus register. 4 rs1 register bank select control bits . the contents of rs1 and rs0 select the working register bank: rs1/rs0 bank selected location 00 bank 0 0x00 C 0x07 01 bank 1 0x08 C 0x0f 10 bank 2 0x10 C 0x17 11 bank 3 0x18 C 0x1f 3 rs0 2 ov overflow flag . 1 C user defined flag . 0 p parity flag, affecte d by hardware to indicate odd or even number of one bits in the accumulator, i.e. even parity. s tack pointer ( sp , sfr 0x8 1 ) : the stack pointer is a 1 - byte register initialized to 0x07 after reset . this register is incremented before push and call instructions, causing the stack to begin at location 0x08. data pointer: the data pointer s ( dptr and dprt1 ) are 2 bytes wide. the lower part is dpl (sfr 0x82) and dpl1 (sfr 0x84), respectively . t he highest is dph (sfr 0x83) and dph1 (sfr 0x85), respectively . the data pointers can be loaded as two registers (e.g. mov dpl,#data8). they are generally used to access external code or data space (e.g. movc a,@a+dptr or movx a,@dptr respectively). program counter: the program counter ( pc ) is 2 bytes wide and initialized to 0x0000 after reset . this register is incremented when fetching operation code or when operating on data from program memory . port registers: segdio0 through segdio15 are controlled by special function registers p0 , p1 , p2 , and p3 as shown in table 14 . a bove segdio15, the lcd _ segdio n [ ] registers in i/o ram are used. since the direction bits are contained in the upper nibble of each sfr pn register and the dio bits are contained in the low er nibble, it is possible to configure the direction of a given dio pin and set its ou t put value with a single write operation, thus facilitating the implementation of bit - banged interfaces. writing a 1 to a dio_dir bit configures the corresponding dio as an output, while writing a 0 configures it as an inp ut. writing a 1 to a dio bit causes the corresponding pin to be at hi gh level (v3p3) , while w riting a 0 causes the corresponding pin to be held at a low level (gnd) . s ee 2.5.10 digital i/o for additional details. downloaded from: http:///
71m6543f/71m6543g data sheet v2 35 table 14 : port registers (segdio0 - 15) sfr name sfr address d7 d6 d5 d4 d3 d2 d1 d0 p0 80 dio_dir[3:0] dio[3:0] p1 90 dio_dir[ 7:4] dio[7:4] p2 a0 dio_dir[ 11 :8] dio[11:8] p3 b0 dio_dir[ 15 : 12 ] dio[15:11] all dio ports on the chip are bi - directional . each of them consists of a l atch (sfr p0 to p3 ) , an output driver and an input buffer, therefore the mpu can output or read data through any of these ports . even if a dio pin is configured as an output, the state of the pin can still be read by the mpu, for example when counting pulses issued via dio pins that are under ce control. at power - up segdio0 - 15 are configured as outputs, but the pins are in a high - impedance state because port_e = 0 ( i/o ram 0x270c[5] ). host firmware should first configure segdio0 - 15 to the desired state, then set port_e = 1 to enable the function. clock stretching ( ckcon[2:0], sfr 0x8e ) the ckcon[2:0] field define s the stretch memor y cycles that are used for movx instructions when access ing external peripherals. the practical value of this register for the 71m6543 is to guarantee access to xram between ce, mpu, and spi . the default setting of ckcon[2:0] (001) should be changed to 000 for best performance. table 15 shows how the signals of the external memory interface change when str etch values are set from 0 to 7. the widths of the signals are counted in mpu clock cycles. the post - reset state of the ckcon[2:0] field (001) , which is shown in bold in the table, performs the movx instructions with a stretch value equal to 1. table 15 : stretch memory cycle width ckcon[2:0] stretch value read s ignal w idth write s ignal w idth memaddr memrd memaddr memwr 000 0 1 1 2 1 001 1 2 2 3 1 010 2 3 3 4 2 011 3 4 4 5 3 100 4 5 5 6 4 101 5 6 6 7 5 110 6 7 7 8 6 111 7 8 8 9 7 2.4.4 instruction set all instructions of the generic 8051 microcontroller are supported . a complete list of the instruction set and of the associated op - codes is contained in the 71m65 4x software users guide (sug) . 2.4.5 uarts the 71m6543 include a uart (uart0) that can be programmed to communicate with a variety of amr modules and other external devices . a second uart (uart1) is connected to the optical port, as described in the 2.5.9 uart and optical interface on page 56 . the uarts are dedicated 2 - wire serial interfaces, which can communicate with an external host processor at up to 38,400 bits/s (with mpu clock = 1.2288 mhz) . the operation of the rx and tx uart0 pins is as follows: downloaded from: http:///
71m6543f/71m6543g data sheet 36 v2 ? uart0 rx: serial input data are applied at this pin . conforming to rs - 232 standard, the bytes are input lsb first. ? uart0 tx : this pin is used to output the serial data . the bytes are output lsb first. the 71m6543 has several uart - related registers for the control and buffering of serial data . a single sfr register serves as both the transmit buffer and receive buf fer ( s0buf , sfr 0x99 for uart0 and s1buf , sfr 0x9c for uart1). when written by the mpu, sxbuf acts as the transmit buffer, and when read by the mpu, it acts as the receive buffer. writing data to the transmit buffer starts the transmission by the associated uart. re ceived data are available by reading from the receive buffer. both uarts can simultaneously transmit and receive data. wdcon [7] (sfr 0xd8) selects whether timer 1 or the internal baud rate generator is used . all uart transfers are pro grammable for parity enable, parity, 2 stop bits/1 stop bit and xon/xo ff options for variable commu nica tion baud rates from 300 to 38400 bps . table 16 shows how the baud rates are calculated . table 17 shows the selectable uart operation modes. table 16 : baud rate generation using timer 1 ( wdcon [7] = 0) using internal baud rate generator ( wdcon [7] = 1) uart0 2 smod * f ckmpu / (384 * (256 - th1 )) 2 smod * f ckmpu /(64 * (2 10 - s0rel )) uart1 n/a f ckmpu /(32 * (2 10 - s1rel )) s0rel and s1rel are 10 - bit values derived by combining bits from the respective timer reload r egisters . ( s0rell, s0relh, s1rell, s1relh are sfr 0xaa, sfr 0xba, sfr 0x9d and sfr 0xbb , respectively) smod is the smod bit in the sfr pcon register ( sfr 0x87 ). th1 (sfr 0x8d) is the high byte of timer 1. table 17 : uart modes uart 0 uart 1 mode 0 n/a start bit, 8 data bits, parity, stop bit, variable baud rate (internal baud rate generator) mode 1 start bit, 8 data bits, stop bit, variable baud rate (internal baud rate generator or timer 1) start bit, 8 data bits, stop bit, variable baud rate (internal baud rate generator) mode 2 start bit, 8 data bits, parity, stop bit, fixed baud rate 1/32 or 1/64 of f ckmpu n/a mode 3 start bit, 8 data bits, parity, stop bit, va riable baud rate (internal baud rate generator or timer 1) n/a parity of serial data is available through the p flag of the accumulator . 7- bit serial modes with parity, such as those used by the flag protocol, can be simulated by setting and reading bit 7 of 8- bit output data . 7- bit serial modes without parity can be simulated by setting bit 7 to a constant 1 . 8- bit serial modes with parity can be simulated by setting and reading the 9 th bit, using the control bits tb80 ( s0con [ 3 ] ) and tb81 ( s1con [3] ) in the s0co n ( sfr 0x98 ) and s1con ( sfr 0x9b ) registers for transmit and rb81 ( s1con [2] ) for receive operations . all supported operation modes use oversampling for the incoming bit stream when r eceiving data. each bit is sampled three times at the projected middle of the bit duration. this technique allows for deviations of the received baud rate from nominal of up to 3.5%. the fe ature of receiving 9 bits (mode 3 for uart0, mode a for uart1) can be used as hands hake signals for inter - processor communication in multi - processor systems. in this case, the slave processors have bit sm20 ( s0con[5] ) for uart0, or sm21 ( s1con[5] for uart1 , set to 1. when the master processor outputs the slaves address, it sets the 9 th bit to 1, causing a serial port receive interrupt in all the slaves. the slave processors compare the received byte with their address. if there is a match, the addressed slave clear s sm20 or sm21 and receive the rest of the message. the rest of the slaves ignore the message. after downloaded from: http:///
71m6543f/71m6543g data sheet v2 37 addressing the slave, the host outputs the rest of the message with the 9 th bit set to 0, so no additional serial port receive interrupts is generated. uart control registers: the function s of uart0 and uart1 depend on the setting of the serial port control register s s0con and s1con shown in table 18 and table 19 , respectively , and the pcon register shown in table 20 . since the ti0 , ri0 , ti1 and ri1 bits are in an sfr bit addressable byte, common practice would be to clear them with a bit operation, but this must be avoid ed . the hardware implements bit operations as a byte wide read - modify - write hardware macro. if an interrupt occurs after the read, but before the write, its flag is cleared un intentionally. the proper way to clear these flag bits is to write a byte mask cons isting of all ones except for a zero in the location of the bit to be cleared. the flag bits are configured in hardware to ignore ones written to them. table 18 : the s0con (uart0) register ( sfr 0x98 ) bit symbol function s0con [7] sm0 the sm0 and sm1 bits set the uart0 mode: mode description sm0 sm1 0 n/a 0 0 1 8- bit uart 0 1 2 9- bit uart 1 0 3 9- bit uart 1 1 s0con [6] sm1 s0con [5] sm20 enables the inter - processor communication feature. s0con[4] ren0 if set, enables serial reception. cleared by software to disable reception. s0con[3] tb80 the 9th transmitted data bit in modes 2 and 3. set or cleared by the mpu, depending on the function it performs (parity check, multiprocessor communication etc.) s0con[2] rb80 in modes 2 and 3 it is the 9 th data bit received. in mode 1, sm20 is 0, rb80 is the sto p bit. in mode 0, this bit is not used. must be cleared by software. s0con[1] ti0 transmit interrupt flag; set by hardware after completion of a serial transfer. must be cleared by software (see caution above) . s0con[0] ri0 receive interrupt flag; set by hardware after completion of a serial rece ption. must be cleared by software (see caution above) . table 19 : the s1con (uart1) register (sfr 0x9b) bit symbol function s1con[7] sm sets the baud rate and mode for uart1. sm mode description baud rate 0 a 9- bit uart variable 1 b 8- bit uart variable s1con[5] sm21 enables the inter - processor communication feature. s1con[4] ren1 if set, enables serial reception. cleared by software to disable reception. s1con[3] tb81 the 9 th transmitted data bit in mode a. set or cleared by the mpu, de pending on the function it performs (parity check, multiprocessor communication etc.) s1con[2] rb81 in modes a and b, it is the 9 th data bit received. in mode b, if sm21 is 0, rb81 is the stop bit. must be cleared by software s1con[1] ti1 transmit interrupt flag, set by hardware after completion of a serial transfer. must be cleared by software (see caution above). s1con[0] ri1 receive interrupt flag, set by hardware after completion of a serial rece ption. must be cleared by software (see caution above). downloaded from: http:///
71m6543f/71m6543g data sheet 38 v2 table 20 : pcon register bit description ( sfr 0x87 ) bit symbol function pcon[7] smod the smod bit doubles the baud rate when set 2.4.6 timers and counters the 80515 has two 16 - bit timer/counter registers: timer 0 and timer 1 . these registers can be configured for counter or timer operations. in timer mode, the register is incremented every machine cycle, i.e. it c ounts up once for every 12 periods of the mpu clock. in counter mode, the register is incremented when the falling edge is observed at the corres ponding input signal t0 or t1 (t0 and t1 are the timer gating inputs derived from certain dio pins, see 2.5.10 digital i/o ). since it takes 2 machine cycles to recognize a 1 - to - 0 event, the maximum input count rate is 1/2 of the cl o ck frequency (ckmpu) . there are no restrictions on the duty cycle, however to ensure proper recognition of the 0 or 1 state, an input should be stable for at least 1 machine cycle. four operating modes can be selected for timer 0 and timer 1, as shown in table 21 and table 22 . the tmod ( sfr 0x89 ) r egister, shown in table 23 , is used to select the appropriate mode. the timer/counter operation is controlled by the tcon ( sfr 0x88 ) r egister, which is shown in table 24 . bits tr1 ( tcon [6] ) and tr0 ( tcon [4] ) in the tcon register start their associated timers when set. table 21 : timers/c ounters mode description m1 m0 mode function 0 0 mode 0 13 - bit counter/timer mode with 5 lower bits in the tl0 or tl1 ( sfr 0x8a or sfr 0x8b ) register and the remaining 8 bits in the th0 or th1 ( sfr 0x8c or sfr 0x8d ) register (for timer 0 and timer 1, respectively) . the 3 high order bits of tl0 and tl1 are held at zero. 0 1 mode 1 16 - bit counter/timer mode . 1 0 mode 2 8- bit auto - reload counter/timer . the reload value is kept in th0 or th1 , while tl0 or tl1 is incremented every machine cycle . when tl( x) overflows, a value from th( x) is copied to tl (x) (where x is 0 for counter/timer 0 or 1 for counter/timer 1 . 1 1 mode 3 if tim er 1 m1 and m0 bits are set to 1, timer 1 stops . if tim er 0 m1 and m0 bits are set to 1, timer 0 acts as two in dependent 8- bit timer/counters. in mode 3, tl0 is affected by tr0 and gate control bits, and sets the tf0 flag on overflow, while th0 is affected by the tr1 bit, and the tf1 flag is set on overflow. table 22 specifies the combinations of operation modes allowed for timer 0 and timer 1. table 22 : allowed timer /counter mode combinations timer 1 mode 0 mode 1 mode 2 timer 0 - mode 0 y es y es y es timer 0 - mode 1 y es y es y es timer 0 - mode 2 not allowed not allowed y es downloaded from: http:///
71m6543f/71m6543g data sheet v2 39 table 23 : tmod register bit description (sfr 0x89) bit symbol function timer/counter 1: tmod[7] gate if tmod[7] is set, external input signal control is enabled for counter 1 . the tr0 bit in the tcon register ( sfr 0x88 ) must also be set in order for counter 0 to increment. with these settings, counter 0 increment s on every falling edge of the logic signal applied to one or more of the segdio2 - 11 pins, as specified by the contents of the dio_r2 through dio_r11 registers. see 2.5.10 digital i/o and lcd segment drivers and table 46 . tmod[6] c/t selects timer or counter operation. when set to 1, a counter operation is performed. when cleared to 0, the corresponding register function s as a timer. tmod[5:4] m1:m0 selects the mode for timer/counter 0 as shown in table 21 . timer/counter 0 tmod[3] gate if tmod[ 3] is set, external input signal control is enabled for counter 0. the tr1 bit in the tcon register ( sfr 0x88 ) must also be set in order for counter 1 to increment. with these settings, counter 1 increment s on every falling edge of the logic signal applied to one or more of the segdio2 - 11 pins, as specified by the contents of the dio_r2 through dio_r11 registers. see 2.5.10 digital i/o and lcd segment drivers and table 46 . tmod[2] c/t selects timer or c ounter operation. when set to 1, a counter operation is performed. when cleared to 0, the corresponding register function s as a t imer. tmod[1:0] m1:m0 selects the mode for timer/counter 1, as shown in table 21 . table 24 : the tcon registe r bit functions (sfr 0x88) bit symbol function tcon[7] tf1 the timer 1 overflow flag is set by hardware when timer 1 overflows. this flag can be cleared by software and is automatically cleared when an interrupt is processed. tcon[6] tr1 timer 1 run control bit. if cleared, timer 1 stops. tcon[5] tf0 timer 0 overflow flag set by hardware when timer 0 overflows. this flag can be cleared by software and is automatically cleared when an interrupt is processed. tcon[4] tr0 timer 0 run control bit. if cleared, timer 0 stops. tcon[3] ie1 interrupt 1 edge flag is set by hardware when the falling edge on external pin int1 is observed. cleared when an interrupt is processed. tcon[2] it1 interrupt 1 type control bit. selects either the falling edge or low level on input pin to cause an interrupt. tcon[1] ie0 interrupt 0 edge flag is set by hardware when the falling edge on external pin int0 is observed. cleared when an interrupt is processed. tcon[0] it0 interrupt 0 type control bit. selects either the falling edge or low level on input pin to cause interrupt. 2.4.7 wd timer (software watchdog timer) there is no int ernal software watchdog timer . use the standard hardware watchdog timer instead (see 2.5.13 hardware watchdog timer ). 2.4.8 interrupts the 80515 provides 11 interrupt sources with four priori ty levels . each source has its own interrupt r equest flag(s) located in a special function register ( tcon , ircon , and scon ) . each interrupt requested by the corresponding flag can be individually enabled or disabled by the enable bits in ien0 (sfr 0xa8) , ien1 (sfr 0xb8) , and ien2 (sfr 0x9a) . figure 12 shows the device interrupt structure. downloaded from: http:///
71m6543f/71m6543g data sheet 40 v2 referring to figure 12 , interrupt sources can originate from within the 80515 mpu core (referred to as in ternal sources) or can originate from other parts of the 71m654 3 soc (referred to as external sources). th ere are seven external interrupt sources, as seen in the leftmost part of figure 12 , and in table 25 and table 26 (i.e., ex0 - ex6 ). i nterrupt overview when an interrupt occurs, the mpu vector s to the predetermined address as shown in table 37 . once the interrupt service has begun, it can be interrupted only by a higher priority inter rupt . the interrupt service is terminated by a return from instruction, reti . when an reti is performed, the processor return s to the instruction that would have been next when the interrupt occurred. when the interrupt condition occurs, the processor also indicate s this by setting a flag bit . this bit is set regardless of whether the interrupt is enabled or disabled . each interrupt flag is sampled once per machine cycle, then samples are polled by the hardware . if the sample indicates a pending interrupt when the interrupt is enabled, then the interrupt request flag is set . on the next instructi on cycle, the interrupt is acknowledged by hardware forcing an lcall to the appropriate vector address, if the foll owing conditions are met: ? no interrupt of equal or higher priority is already in progress. ? an instruction is currently being executed and is not completed. ? the instruction in progress is not reti or any write access to the r egisters ien0 , ien1 , ien2 , ip0 or ip1 . special function registers for interrupts the following sfr registers control the interrupt functions: ? the interrupt enable registers : ien0, ien1 and ien2 (see table 25 , table 26 and table 27 ). ? the timer/counter control registers, tcon and t2con (see table 28 and table 29 ). ? the interrupt request r egister , ircon (see table 30 ). ? the interrupt priority regis ters: ip0 and ip1 (see table 35 ). table 25 : the ien0 bit functions (sfr 0xa8) bit symbol function ien0 [7] eal eal = 0 disable s all interrupts . ien0 [6] C not used . ien0 [5] C not used . ien0 [4] es0 es0 = 0 disable s serial channel 0 interrupt . ien0 [3] et1 et1 = 0 disable s timer 1 overflow interrupt . ien0 [2] ex1 ex1 = 0 disable s external interrupt 1 . ien0 [1] et0 et0 = 0 disable s timer 0 overflow interrupt . ien0 [0] ex0 e x0 = 0 disable s external interrupt 0 . table 26 : the ien1 bit functions (sfr 0xb8) bit symbol function ien1 [7] C not used. ien1 [6] C not used. ien1 [5] ex6 ex6 = 0 disable s external interrupt 6 . ien1 [4] ex5 ex5 = 0 disable s external interrupt 5 . ien1 [3] ex4 ex4 = 0 disable s external interrupt 4 . ien1 [2] ex3 ex3 = 0 disable s external interrupt 3 . ien1 [1] ex2 ex2 = 0 disable s external interrupt 2 . ien1 [0] C not u sed. downloaded from: http:///
71m6543f/71m6543g data sheet v2 41 table 27 : the ien2 bit functions (sfr 0x9a) bit symbol function ien2[0] es1 es1 = 0 disable s the serial channel 1 interrupt . table 28 : tcon bit functions (sfr 0x88) bit symbol function tcon[7] tf1 timer 1 overflow flag . tcon[6] tr1 not used for interrupt control . tcon[5] tf0 timer 0 overflow flag . tcon[4] tr0 not used for interrupt control . tcon[3] ie1 external interrupt 1 flag . tcon[2] it1 external interrupt 1 type control bit : 0 = interrupt on low level. 1 = interrupt on falling edge. tcon[1] ie0 external interrupt 0 flag tcon[0] it0 external interrupt 0 type control bit : 0 = interrupt on low level. 1 = interrupt on falling edge. table 29 : the t2con b it functions (sfr 0xc8) bit symbol function t2con[7] C not used. t2con[6] i3fr polarity control for int3: 0 = falling edge. 1 = rising edge. t2con[5] i2fr polarity control for int2: 0 = falling edge. 1 = rising edge. t2con[4:0] C not used. table 30 : the ircon bit functions (sfr 0xc0) bit symbol function ircon[7] C not used . ircon[6] C not used . ircon[5] iex6 1 = external interrupt 6 flag . irco n[4] iex5 1 = external interrupt 5 flag. ircon[3] iex4 1 = external interrupt 4 flag. ircon[2] iex3 1 = external interrupt 3 flag. ircon[1] iex2 1 = external interrupt 2 flag. ircon[0] C not used. tf0 and tf1 (timer 0 and timer 1 overflow flag s ) is automatically cleared by hardware when the service routine is called (signals t0ack and t1ack C port isr C active high when the service routine is called). ie0, ie1 , and iex2 - iex6 are cleared automatically when hardware causes execution to vector to the interrupt service routine. downloaded from: http:///
71m6543f/71m6543g data sheet 42 v2 external mpu interrupts the seven external interrupts are the interrupts external to the 80515 core, i .e. signals that originate in other parts of the 71m6543 , for example the ce, dio, rtc , or eeprom interface. the external interrupts are connected as shown in table 31 . the po larity of in terrupts 2 and 3 is programmable in the mpu via the i3fr and i2fr bits in t2con (sfr 0xc8) . interrupts 2 and 3 should be programmed for falling sensitivity ( i3fr = i2fr = 0). the generic 8051 mpu literature states that interrupts 4 through 6 are defined as rising - edge sensitive. thus, the hardware signals attached to interrupts 5 and 6 are in verted to achieve the edge polarity shown in table 31 . table 31 : external mpu interrupts external interrupt connection polarity flag reset 0 digital i/o (ie0) see 2.5.10 automatic 1 digital i/o (ie1) see 2.5.10 automatic 2 ce_pulse (ie_xpulse, i e _ypulse, ie_wpulse, ie_vpulse) rising manual 3 ce_busy (ie3) falling automatic 4 vstat ( vstat[2:0] changed ) (ie4) rising automatic 5 eeprom busy (falling), spi (rising) (ie_eex, ie_spi) manual 6 xfer_busy (falling), rtc_1sec, rtc_1min, rtc_ t (ie_xfer, ie_rtc1s, ie_rtc1m, ie_rtct) falling manual external interrupt 0 and 1 can be mapped to pins on the device using dio reso urce maps. see 2.5.10 digital i/o for more information. sfr enable bits must be set to permit any of these interrupts to occur . likewise, each interrupt has its own flag bit, which is set by the interrupt hardware, and reset by t he mpu interrupt handler . xfer_busy, rtc_1sec, rtc_1min , rtc_ t , spi, pllrise and pllfall have their own enable and flag bits in addition to the interrupt 6, 4 and enable and flag bits (see table 32 : interrupt enable and flag bits ). ie0 through iex6 are cleared automatically whe n the hardware vectors to the interrupt handler . the other flags, ie_xfer through ie_ vpulse , are cleared by writing a zero to them . since these bits are in an sfr bit addressable byte, common practice would be to clear them with a bit operation, but thi s must be avoided . the hardware implements bit operations as a byte wide read - modify - write hardware macro . if an interrupt occurs after the read, but before the write, its flag is cleared un intentionally . the proper way to clear the flag bits is to write a byte mask cons isting of all ones except for a zero in the location of the bit to be cleared . the flag bits are configured in hardware to ignore ones written to them. table 32 : interrupt enable and flag bits interrupt enable interrupt flag interrupt description n ame l ocation name location ex0 sfr a8[[0] ie0 sfr 88[1] external interrupt 0 ex1 sfr a8[2] ie1 sfr 88[3] external interrupt 1 ex2 sfr b8[1] iex2 sfr c0[1] external interrupt 2 ex3 sfr b8[2] iex3 sfr c0[2] external interrupt 3 ex4 sfr b8[3] iex4 sfr c0[3] external interrupt 4 ex5 sfr b8[4] iex5 sfr c0[4] external interrupt 5 ex6 sfr b8[5] iex6 sfr c0[5] external interrupt 6 ex_xfer ex_rtc1s 2700[0] 2700[1] ie_xfer ie_rtc1s sfr e8[0] sfr e8[1] xfer_busy interrupt (int 6) rtc_1sec interrupt (int 6) downloaded from: http:///
71m6543f/71m6543g data sheet v2 43 interrupt enable interrupt flag interrupt description n ame l ocation name location ex_rtc1m ex_rtc t ex_spi ex_eex ex_xpulse ex_ypulse ex_wpulse ex_vpulse 2700[2] 2700[4] 2701[7] 2700[7] 2700[6] 2700[5] 2701[6] 2701[5] ie_rtc1m ie_rtc t ie_spi ie_eex ie_xpulse ie_ypulse ie_wpulse ie_vpulse sfr e8[2] sfr e8[4] sfr f8[7] sfr e8[7] sfr e8[6] sfr e8[5] sfr f8[ 6] sfr f8[ 5] rtc_1min interrupt (int 6) rtc_ t interrupt (int 6) spi interrupt eeprom interrupt ce_xpulse interrupt (int 2) ce_ypulse interrupt (int 2) ce_wpulse interrupt (int 2) ce_vpulse interrupt (int 2) interrupt priority level structure all interrupt sources are combined in groups, as shown in table 33 . table 33 : interrupt priority level groups group group members 0 external interrupt 0 serial channel 1 interrupt 1 timer 0 interrupt external interrupt 2 2 external interrupt 1 external interrupt 3 3 timer 1 interrupt external interrupt 4 4 serial channel 0 interrupt external interrupt 5 5 C external interrupt 6 each group of interrupt sources can be programmed individually to one of four pri ority levels (as shown in table 34 ) by setting or clearing one bit in the sfr interrupt priority register ip0 ( sfr 0xa9 ) and one in ip1 (sfr 0xb9) ( table 35 ). if requests of the same priority level are received simultaneously, an int ernal polling sequence as shown in table 36 determines which request is serviced first. changing interrupt priorities while interrupts are enabled can easily caus e software defects. it is best to set the interrupt priority registers only once during initializa tion before interrupts are enabled. table 34 : interrupt priority levels ip1 [x] ip0 [x] priority level 0 0 level 0 (lowest) 0 1 level 1 1 0 level 2 1 1 level 3 (highest) table 35 : interrupt priority registers ( ip0 and ip1 ) register address bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) ip0 sfr 0xa9 C C ip0[5] ip0[4] ip0[3] ip0[2] ip0[1] ip0[0] ip1 sfr 0xb9 C C ip1[5] ip1[4] ip1[3] ip1[2] ip1[1] ip1[0] downloaded from: http:///
71m6543f/71m6543g data sheet 44 v2 table 36 : interrupt polling sequence external interrupt 0 polling sequence serial channel 1 interrupt timer 0 interrupt external interrupt 2 external interrupt 1 external interrupt 3 timer 1 interrupt external interrupt 4 serial channel 0 interrupt external interrupt 5 external interrupt 6 interrupt sources and vectors table 37 shows the interrupts with their associated flags and vector addresses. table 37 : interrupt vectors interrupt request flag description interrupt vector address ie0 external interrupt 0 0x0003 tf0 timer 0 interrupt 0x000b ie1 external interrupt 1 0x0013 tf1 timer 1 interrupt 0x001b ri0/ti0 serial channel 0 interrupt 0x0023 ri1/ti1 serial channel 1 interrupt 0x0083 iex2 external interrupt 2 0x004b iex3 external interrupt 3 0x0053 iex4 external interrupt 4 0x005b iex5 external interrupt 5 0x0063 iex6 external interrupt 6 0x006b downloaded from: http:///
71m6543f/71m6543g data sheet v2 45 figure 12 : interrupt structure downloaded from: http:///
71m6543f/71m6543g data sheet 46 v2 2.5 on - chip resources 2.5.1 physical memory 2.5.1.1 flash memory the device includes 64 kb (71m6543f) or 128 kb (71m6543g) of on - chip flash memory. the flash memory primarily contains mpu and ce program code. it also contains images of the ce ram and i/o ram. on power - up, before enabling the ce, the mpu copies these images to their respective loc ations. f lash space allocated for the ce program is limited to 4096 16 - bit words ( 8 kb). t he ce program must begin on a 1 - kb boundary of the flash address space. the ce_lctn[6/5:0] ( i/o ram 0x2109[5:0] ) field on the 71m6543f and the ce_lctn[ 6 :0] ( i/o ram 0x2109[6 :0] ) field on the 71 m6543g define which 1 - kb boundary contains the ce code. thus, the first ce instruction is located at 1024* ce_lctn[6/5:0] on the 71m6543f and at 1024* ce_lctn[ 6 :0] on the 71m6543g. flash memory can be accessed by the mpu, the ce, and by the spi interface (r/w). table 38 : flash memory access access by access type condition mpu r/w/e w/e only if ce is disabled. ce r spi r/w /e access only when sfm is invoked (mpu halted). flash write procedures if the flsh_unlock [3:0] (i/o ram 0x2702[7:4]) key is correctly programmed, the mpu may write to the flash memory. this is one of the non - volatile storage options available to the user in addition to external eeprom. the flash program write enable bit, flsh_pstwr (sfr 0xb2[0]), differentiates 80515 d ata store instructions (movx@dptr,a) between flash and xram writes. this bit is automati cally cleared by hardware after each byte write operation. write operations to this bit are inhibited when interrupts are enabled. if the ce is enabled ( ce_e = 1 , i/o ram 0x2106[0] ), flash write operations must not be attempted unless flsh_ pstwr is set. this bit enables the posted flash write capability. flsh_ pstwr ha s no effect when ce_e = 0). when ce_e = 1, however, flsh_ pstwr delay s a flash write until the time interval between the ce code passes. during this delay time, the flsh_pend ( sfr 0xb2[3] ) bit is high, and the mpu continue s to execute commands. when the ce code pass ends (ce_busy falls), the flsh_pend bit fall s and the write operation occur s . the mpu can query the flsh_pend bit to determine when the write operation has been completed. while flsh_pend = 1, further flash write re quests are ignored. updating individual bytes in flash m emory the original state of a flash byte is 0xff (all b its are 1 ). once a value other than 0xff is written to a flash memory cell, over writing with a different value usually requires that the cell be eras ed first. since cells cannot be erased individually, the page has to be first copied to ram, followed by a page erase. after this, the page can be updated in ram and then written back to the flash memory. flash erase procedures flash erasure is initiated by writing a specific data pattern to sp ecific sfr registers in the proper sequence. these special pattern/sequence requirements prevent inadvertent erasure of the flash memory. the mass erase sequence is: ? write 1 to the flsh_meen bit ( sfr 0xb2[1] ). ? write the pattern 0xaa to the flsh_erase ( sfr 0x94 ) register . the mass erase cycle can only be initiated when the ice port is enabled. downloaded from: http:///
71m6543f/71m6543g data sheet v2 47 the page erase sequence is: ? write the page address to flsh_pgadr [5 :0] ( sfr 0xb7[7: 2]) . ? write the pattern 0x55 to the flsh_erase register ( sfr 0x94 ). bank - switching in the 71m6543g the 128 kb program memory in the 71m6543g consists of a fixed lower bank of 32 kb, addressable at 0x0000 to 0x7fff plus an upper banked area of 32 kb, addressable at 0x8000 to 0xffff. t he i/o ram register fl_bank [1:0] (sfr 0xb6[1:0]) is used to switch four memory banks of 32 kb each into the address range from 0x8000 to 0xffff. note that when fl_bank[1:0] (sfr 0xb6[1:0]) = 0, the upper bank is the same as the lower bank. table 39 : bank switching with fl_bank[1:0] (sfr 0xb6[1:0]) in the 71m6543g 71m6543g fl_bank[ 1:0] address range for lower bank (0x0000 - 0x7fff) address range for upper bank (0x8000 - 0xffff) 00 0x0000 - 0x7fff 0x0000 - 0x7fff 01 0x0000 - 0x7fff 0x8000 - 0xffff 10 0x0000 - 0x7fff 0x10000 - 0x17fff 11 0x0000 - 0x7fff 0x18000 - 0x1ffff in the 71m6543g, t he address that the flsh_pgadr[6:0] (sfr 0x b7[7:1]) points to in the program address space can reference different flash memory locations, depending on the sett ing of the fl_bank[1:0] (sfr 0x b6[1:0]) bits. the ce_lctn[ 6 :0] ( i/o ram 0x2109[6 :0] ) field on the 71m6543g on the other hand, point s directly to a location in the flash memory are not affected by the fl_bank[1:0] (sfr 0x b6[1:0]) bits program security when enabled, the security feature limits the ice to global flash erase operations onl y. all other ice operations, such as reading via the spi or ice port, are blocked. this guarantees the security of the users mpu and ce program code. security is enabled by mpu code that is executed in a 64 ckmpu cycle pre - boot interval before the primary boot sequence begins. once security is enabled, the only way to disable it is to perform a global erase of the flash, followed by a chip r eset. the first 64 cycles of the mpu boot code are called the pre - boot phase because during this phase the ice is inhibited. a read - only status bit, preboot (sfr 0xb2[7]) , identifies these cycles to the mpu. upon completion of pre - boot, the ice can be enabled and is permitted to take control of the mpu. t he security en able bit, secure (sfr 0xb2[6]) , is reset whenever the chip is reset. hardwar e associated with the bit allow s only ones to be written to it. thus, pre - boot code may set secure to enable the security feature but may not reset it. once secure is set, the p re - boot and ce code are protected from e r asure, and no external read of program code is possible . specifically, when the secure bit is set , the following applies : ? the ice is limited to bulk flash erase only. ? page zero of flash memory, the preferred location for the users pre - boot code, may not be page - erased by either mpu or ice. page zero may only be erased with global fl ash erase. ? write operation s to page zero, whether by mpu or ice are inhibited. the 71m6543 also includes hardware to protect against unintentional flash write and erase. to enabl e flash write and erase operations, a 4 - bit hardware key that must be written to the flsh_unlock[3:0] field . the key is the binary number 0010. if flsh_ unlock[3:0] is not 0010, the flash erase and write operation is inhibited by hardware. proper operation of this security key requires that there be no firmware function that writes 0010 to flsh_unlock[3:0] . the key should be written by the external spi master, in the case of spi flash programming (sfm mode), or through the ice interface in the case of ice flash programming. when a boot loader is used, the key should be sent to the boot load code which then writes it to downloaded from: http:///
71m6543f/71m6543g data sheet 48 v2 flsh_unlock[3:0]. flsh_unlock[ 3:0] is not automatically reset. it should be cleared when the spi or ice has finished changing the flash. table 40 summarizes the i/o ram registers used for flash security. table 40 : flash security name location rst wk dir description flsh_unlock[3:0] 2702[7:4] 0 0 r/w must be a 2 to enable any flash modification. see the description of flash security for more details. secure sfr b2[6] 0 0 r/w inhibits erasure of page 0 and flash addresses above the beginning of ce code as defined by ce_lctn[6/5:0] (i/o ram 0x2109[5:0]) on the 71m6543f and ce_lctn[ 6:0] i/o ram 0x2109[6:0]) o n the 71m6543g . also inhibits the read of flash via the ice and spi ports. spi flash mode in normal operati on, the spi slave interface can not read or write the flash memory. however, the 71m6543 contains a special flash mode (sfm) that facilitates initial (production) programming of the flash memory. when the 71m6543 is in sfm mode, the spi interface can erase, read, and write the flash. other memory elements such as xram and i / o ram are not accessible to the spi in this mode. in order to protect the flash contents, several operations are required before the sfm mode is successfully invoked. when the 71m6543g is operating sfm, spi single - byte transactions are used to write to fl_bank[1:0] (sfr 0xb6[1:0]) . during an spi single - byte transaction, spi_cmd[1:0] will over -w rite the contents of fl_bank[1:0] (sfr 0xb6[1:0]) . this will allow for access of the entire 128 kb flash memory w hile operating in sfm. if the spi port is used for code updates (in lieu of a programmer that uses t he ice port), then a code that disables the flash access via spi can potentially lock out flash program updates. details on the sfm ca n b e found in 2.5.12 spi slave port . 2.5.1.2 mpu/ce ram the 71m6543 includes 5 kb of static ram memory on - chip (xram) plus 256 bytes of internal ram in the mpu core. the 5kb of sta tic r am are used for data storage by both mpu and ce and f o r the com munica tion between mpu and ce . 2.5.1.3 i/o ram (configuration ram) the i/o ram can be seen as a series of hardware registers that control basic hardware functions. i/o ram address space starts at 0x2000. the registers of the i/o ram are listed in table 68 . the 71m6543 includes 128 bytes non - volatile ram memory on - chip in the i/o ram address sp ace (addresses 0x2800 to 0x287f). this memory section is supported by the volt age applied at vbat_rtc , and the data in it are preserved in brn , lcd, and slp modes as long as the voltage at vbat_rtc is within specification. 2.5.2 oscillator the 71m6543 oscillator drives a standard 32.768 khz watch crystal . this type of crystal is accurate and does not require a high - current oscillator circuit . the oscillator has been designed specifically to handle watch crystals and is compatible with their high impedance and limited power handling capability. the oscillator p ower dissipation is very low to maximize the lifetime of any b attery attached to vbat _rtc . oscillator calibration can improve the accuracy of both the rtc and metering. refer to 2.5.4 , real - time clock (rtc) for more information. the oscillator is powered from the v3p3sys pin or from the vbat_rtc pi n, depending on the v3ok in ternal bit (i.e., v3ok = 1 if v3p3sys 2.8 vdc and v3ok = 0 if v3p3sys < 2.8 vdc). the oscillator requires approximately 100 na, which is negligible compared to the internal leakage of a battery. downloaded from: http:///
71m6543f/71m6543g data sheet v2 49 although the oscillator may appear to work when vbat is not connected, this m ode of operation is not re - commended. if vbat_rtc is connected to a drained battery or disconnected, a battery test that sets temp_bat ma y drain the supply connected to vbat_rtc and cause the oscillator to stop. a stopped oscillator may force the device to reset. therefore, an unexpected reset during a battery test should be interpreted as a battery failure. 2.5.3 pll and internal clocks timing for the device is derived from the 32.768 khz crystal oscillator output that is multiplied by a pll by 600 to obtain 19.660800 mhz, the master clock (mck) . all o n- chip timing, except for the rtc clock, is derived from mck. table 41 provides a summary of the clock functions and their controls . the two general - purpose counter/timers contained in the mpu are controlled by ckmpu (see 2.4.6 timers and counters ). the master clock can be boosted to 19.66 mhz by setting the pll_fast bit = 1 ( i/o ram 0x2200[4] ) and can be reduced to 6.29 mhz by pll_fast = 0. the mpu clock frequency ckmpu is determined by another divider controlled by the i/o ram control field mpu_div [2:0] (i/o ram 0x2200[2:0]) and can be set to mck*2 -( mpu_div +2) where mpu_div [2:0] may vary from 0 to 4 . when the ice_e pin is high, t he cir cuit also generates the 9.8 3 mhz clock for use by the emul ator. the pll is only turned off in slp mode or in lcd mode when lcd_bste is disabled. the lcd_bste value depends on the setting of the lcd_vmode [1:0] field (see table 51 ). when the part is waking up from slp or lcd modes, the pll is turned on in 6.29 mhz mode, and the pll frequency is not be accurate until the pll_ok ( sfr 0xf9[4] ) flag rises. due to potential overshoot, the mpu should not change the value of pll_fast until pll_ok is true. table 41 : clock system summary clock derived from fixed frequency or range function pll_fast =1 pll_fast =0 controlled by osc crystal 32.768 khz C crystal clock mck crystal/pll 19.660800 mhz (600*ck32) 6.291456 mhz (192*ck32) pll_fast master clock ckce mck 4.9152 mhz 1.5728 mhz C ce clock ckadc mck 4.9152 mhz, 2.4576 mhz 1.572864 mhz, 0.786432 mhz adc_div adc clock ckmpu mck 4.9152 mhz 307.2 khz 1.572864 mhz 98.304 khz mpu_div [2:0] mpu clock ckice mck 9.8304 mhz 614.4 khz 3.145728 mhz 196.608 khz mpu_div[2:0] ice clock ckoptmod mck 38.40 khz 38.6 khz C optical uart modulation ck32 mck 32.768 khz C 32 khz clock 2.5.4 real - time clock (rtc) 2.5.4.1 rtc general description the rtc is driven directly by the crystal oscillator and is powered by either the v3p3sys pin or the vbat_rtc pin , depending on the v3ok internal bit. the rtc consists of a counter chain and output reg isters. the counter chain consists of registers for seconds, minutes , hours, day of week, day of month, month, and year. the chain registers are supported by a shadow regist er that facilitates read and write operations. table 42 shows the i/o ram registers for accessing the rtc. downloaded from: http:///
71m6543f/71m6543g data sheet 50 v2 2.5.4.2 accessing the rtc two bits, rtc_rd (i/o ram 0x2890[6] ) and rtc_wr (i/o ram 0x2890[7]) , control the behavior of the shadow register. when rtc_rd is low, the shadow register is updated by the rtc after each two mill iseconds. when rtc_rd is high, this update is halted and the shadow register contents beco me stationary and are suitable to be read by the mpu. thus, when the mpu wishes to read the rtc, it freeze s the shadow register by setting the rtc_rd bit, read s the shadow register, and then lower s the rtc_rd bit to let updates to the shadow register resume. since the rtc clock is only 500 hz, there may be a delay of approxim ately 2 ms from when the rtc_rd bit is lowered until the shadow register receives its first update. reads to rtc_rd continue s to return a one until the first shadow update occurs. when rtc_wr is high, the update of the shadow register is also inhibited. during thi s time, the mpu may overwrite the contents of the shadow register. when rtc_wr is lowered, the shadow register is written into the rtc counter on the next 500hz rtc clock. a change bit is included for each word in the shadow register to ensure that only programmed words are updated when the mpu writes a zero to rtc_wr . reads of rtc_wr return s one until the counter has actually been updated by the register. the sub - second register of the rtc, rtc_sbsc (i/o ram 0x2892) , can be read by the mpu after the one second interrupt and before reaching the next one second boundary. rtc_sbsc contai ns the count since the last full second , in 1/128 second nominal clock periods, until the next one - second boundary. when the rst_subsec bit is written, the subsec counter is restarted, counting from 0 to 127. reading and resetting the sub - second counter can be used as part of an algorithm to accurately set the rt c. the rtc is capable of processing leap years. each counter has its own outp ut register. the rtc chain registers are not be affected by the reset pin, watchdog timer resets, or by transiti ons between the battery modes and mission mode. table 42 : rtc control registers name location rst wk dir description rtc a _adj[6:0] 2504 [6:0] 40 -- r/w register for analog rtc frequency adjust ment . rtc_p[16:14] rtc_p[13:6] rtc_p[5:0] 289b[2:0] 289c[7:0] 289d[7:2] 4 0 0 4 0 0 r/w registers for digital rtc adjust ment. 0x0ffbf rtc_p 0x10040 rtc_q[1:0] 289d[1:0] 0 0 r/w register for digital rtc adjust ment. rtc_rd 2890[6] 0 0 r/w freezes the rtc shadow register so it is suitable for mpu reads. when rtc_rd is read, it returns the status of the shadow register: 0 = up to date, 1 = frozen. writing 0 to rtc_rd bit to enable shadow register update, and writing 1 to rtc_rd to disable update rtc_wr 2890[7] 0 0 r/w freezes the rtc shadow register so it is suitable for mpu write operation s. when rtc_wr is cleared, the contents of the shadow register are written to the rtc counter on the next rtc clock (~1 khz). when rtc_wr is read, it return s 1 as long as rtc_wr is set, and continue s to return one until the rtc counter is up dated . writing 0 to rtc_wr bit to enable copying the shadow register contents t o rtc counter, and writing 1 to rtc_wr to disable copying rtc_fail 2890[4] 0 0 r/w indicates that a count error has occurred in the rtc and that the time is not trustworthy. this bit can be cleared by writing a 0 . rtc_sbsc[7:0] 2892[7:0] r time remaining since the last 1 second boundary. lsb = 1/128 second. downloaded from: http:///
71m6543f/71m6543g data sheet v2 51 2.5.4.3 rtc rate control the 71m6543 has two rate adjustment mechanisms: ? the first rate adjustment mechanism is an analog rate adjustment, using the i/o ram register rtca_adj[6:0] , that trims the crystal load capacitance. ? the second rate adjustment mechanism is a digital rate adjust that affects the way the clock frequency is processed in the rtc. setting rtca_adj[6:0] to 00 minimizes the load capacitance, maximizing the oscillator frequency . setting rtca_adj[6:0] to 0x7f maximizes the load capacitance, minimizing the oscillator frequency. the adjustable capacitance is approximately: pf adj rtca c adj 5.16 128 _ ? = the precise amount of adjustment depend s on the crystal properties, the pcb layout and the value of the external crystal capacitors (see cx s and cxs in table 87 ) . the adjustment may occur at any time, and the result ing clock frequency should be measured over a one - second interval. the second rate adjustment is digital, and can be used to adjust the clock rate up to 988ppm, with a resolution of 3.8 ppm. the rate adjustment is implemented starting at the next second - boundary fol lowing the adjustment . since the lsb (define first) results in an adjustment every four seconds, the frequency should be measured over an interval that is a multiple of four seconds. the clock rate is adjusted by writing the appropriate values to rtc_p[ 16:0] ( i/o ram 0x289b[2:0], 0x289c, 0x289d[7:2] ) and rtc_q[1:0] (i/o ram 0x289d[1:0]) . updates to rtc rate adjust registers, rtc_p and rtc_q , are done through the shadow register described above. the new values are load ed into the counters when rtc_wr (i/o ram 0x2890[7] ) is lowered. the default frequency is 32,768 rtclk cycles per second. to shift the clock frequency by ? ppm, rtc_p and rtc_q are calculate d using the following equation: ?? ? ?? ? + ?? + ? = + ? ? 5.0 10 1 8 32768 rtc_q rtc_p 4 6 floor co nversely, the amount of ppm shift for a given value of 4rtc_p + rtc_q is: 6 10 1 4 8 32768 ) ( ? ? ?? ? ? ?? ? ? + ? ? = ? q p rtc rtc ppm for example, for a shift of - 988 ppm, 4 ? rtc_p + rtc_q = 262403 = 0x40103. rtc_p [16:0] = 0x10040, ( i/o ram 0x289b[2:0], 0x289c, 0x289d[7:2] ) and rtc_q [1:0] = 0x03 ( i/o ram 0x289d[1:0] . the default values of rtc_p [16:0] and rtc_q [1:0] , corresponding to zero adjustment, are 0x10000 and 0x0, respectively . two settings for the tmux2out test pin, pulse_1s and pulse_4s, are availabl e for measuring and calibrating the rtc clock frequency. these are waveforms of approximately 25% duty cycle with 1s or 4s period. default values for rtc a _adj [6:0] , r tc_p [16:0] and r tc_q [1:0] should be nominal values, at the center of the ad just ment range. un - calibrated extreme values (zero , for example) can cause incorrect operation. if the crystal temperature coefficient is known, the mpu can integrate temperat ure and correct the rtc time as necessary. alternatively, the characteristics can be loaded int o an nv ram and the osc_comp ( i/o ram 0x28a0[5 ]) bit may be set. in this case, the oscillator is adjusted automatically, even in slp mode. see 2.5.4.4 rtc temperature compensation for details. downloaded from: http:///
71m6543f/71m6543g data sheet 52 v2 2.5.4.4 rtc temperature compensation t he 71m6543 can be configured to regularly measure die temperature, including in slp and lcd modes and while the mpu is halted. if enabled by osc_comp , this temperature information is auto matically used to correct for the temperature variation of the crystal. a table lookup method is used . table 43 shows i/o ram registers in volved in automatic rtc temperature compensation. table 43 : i/o ram registers for rtc temperature compensation name location rst wk dir description osc_comp 28a0[5] 0 0 r/w enables the automatic update of rtc_p [16:0] and rtc_q [1:0] every time the temperature is measured. stemp[10:3] stemp[2:0] 2 881[7:0 ] 2 88 2 [7:5 ] C C r th e re s ult of the temperature measure ment (10 - bits of magnitude data plus a sign bit) . lkpaddr[6:0] 2887[6:0] 0 0 r/w the address for reading and writing the rtc lookup ram. lkpautoi 2887[7] 0 0 r/w auto - increment flag. when set, lkpaddr [6:0] auto increment s every time lkp_rd or lkp_wr is pulsed. the incremented address can be read at lkpaddr [6:0] . lkpdat[7:0] 2888[7:0] 0 0 r/w the data for reading and writing the rtc lookup ram. lkp_rd lkp_wr 2889[1] 2889[0] 0 0 0 0 r/w r/w strobe bits for the rtc lookup ram read and write. when set, the lkpaddr [6:0] and lkpdat registers are used in a read or write operation. when a strobe is set, it stay s set until the operation completes, at which time the strobe is cleared and lkpaddr [6:0] is incremented if lkpautoi is set. referring to figure 13 the table lookup method uses the 10 - bits plus sign - bit value in stemp [10:0] right - shifted by two bits to obtain an 8 - bit plus sign value (i.e., nv ram address = stemp [10:0] /4). a limiter ensures that the resulting look - up address is in the 6 - bit plus sign range of - 64 to +63 (decimal). the 8 - bit nv ram content pointed to by the address is added as a 2s complement value to 0x40000, the nominal val ue of 4* rtc_p [16:0] + rtc_q [1:0] . refer to 2.5.4.3 rtc rate control for information on the rate adjustments performed by registers rtc_p [ 16:0] and rtc_q [ 1:0] . the 8 - bit values loaded in to nv ram must be scaled correctly to produce rate adjustments that are consistent with the equations given in 2.5.4.3 rtc rate control for rtc_p [16:0] and rtc_q [1:0] . note that the sum of the looked - up 8 - bit 2s complement value and 0x40000 form a 19 - bit value, which is equal to 4* rtc_p [16:0] + rtc_q [1:0] , as shown in figure 13 . the output of the temperature compensation is automatically loaded into the rtc_p[16:0] and rtc_q[1:0] locations after each look - up and summation operation. 0x40000 19 10+s stemp >>2 63 -64 -64 63 255 -256 limit look up ram addr 6+s 8+s q 7+s 4*rtc_p+rtc_q 19 figure 13 : automatic temperature compensation the 128 nv ram locations are organized in 2s complement format . as mentioned above, the stemp [10:0] digital temperature values are scaled such that the corresponding nv ram addresses are equal to stemp [10:0] /4 (limited in the range of - 64 to +63) . see 2.5.5 71m6543 temperature sensor on page 53 for the equations to calculate temperature in degrees c from the stemp[10:0] reading. downloaded from: http:///
71m6543f/71m6543g data sheet v2 53 for proper operation, the mpu has to load the lookup table with values that refl ect the crystal properties with respect to temperature, which is typically done once during initi alization. since the lookup table is not directly addressable, the mpu uses the following procedure to load the nv ram table: 1. set the lkpautoi bit ( i/o ram 0x2887[7] ) to enable address auto - increment . 2. write zero into the i/o ram register lkpaddr[6:0] ( i/o ram 0x2887[6:0] ). 3. write the 8 - bit dat um into i/o ram register lkpdat ( i/o ram 0x2888 ). 4. set the lkp_wr bit ( i/o ram 0x2889[0 ] ) to write the 8 - bit datum into nv_ram 5. wait for lkp_wr to clear ( lkp_wr auto - clears when the data has been copied to nv ram) . 6. repeat steps 3 through 5 until all data has been written to nv ram. the nv ram t able can also be read by writing a 1 into the lkp_rd bit ( i/o ram 0x2889[1] ). the process of reading from and writing to the nv ram is accelerated by setting the lkpautoi bit ( i/o ram 0x2887[7] ). when lkpautoi is set, lkpaddr[6:0] ( i/o ram 0x2887[6:0] ) auto - increment s every time lkp_rd or lkp_wr is pulsed. it is also possible to perform random access of the nv ram by writing a 0 to the lkpautoi bit and loading the desired address into lkpaddr[6:0] . if the oscillator temperature compensation feature is not being used, it is possible to use the nv ram storage area as ordinary battery - backed nv storage space using the procedure described above to read and write nv ram data. in this case, the osc_comp bit ( i/o ram 0x28a0[5] ) is reset to disable the automatic oscillator temperature compensation feature. 2.5.4.5 rtc interrupts the rtc generates interrupts each second and each minute. these interrupts are called rtc_1sec and rtc_1min . in addition, the rtc functions as an alarm clock by generating an interrupt when the mi nutes and hours register s both equal their respective target count s as defined in table 44 . the alarm clock interrupt is called rtc_ t. all three interrupts appear in the mpus external interrupt 6. see table 32 in the interrupt section for the enable bit s and flags for these interrupts. the minute and hour target registers are listed in table 44 . table 44 : i/o ram registers for rtc interrupts name location rst wk dir description rtc_tmin[5:0] 289e[5:0] 0 0 r/w the target minutes register. see below. rtc_thr[4:0] 289f[4:0] 0 0 r/w the target hours register. the rtc_ t interrupt occur s when rtc_min [5:0] becomes equal to rtc_tmin [5:0] and rtc_hr [4:0] becomes equal to rtc_thr [4:0] . 2.5.5 71m6543 temperature sensor the 71m6543 includes an on - chip temperature sensor for determining the temperature of its bandgap re ference . the primary use of the temperature data is to determine the magnitude of compensation re quired to offset the th ermal drift in the system for the com pensa tion of current, voltage and energy measurement and the rtc . s ee 4.5 metrology temperature compensation on page 88 . also see 2.5.4.4 rtc temperature compensa tion on page 52 . unlike earlier generation maxim socs, t he 71m 6543 does not use the adc to read the temperature sensor. instead, it uses a technique that is operation al in slp and lcd mode, as well as brn and msn modes. this means that the temperature sensor can be used to compensate for the frequency variation o f the crystal, even in slp mode while the mpu is halted. see 2.5.4.4 rtc temperature compensation on page 52 . in msn and brn modes, the temp erature sensor is awakened on command from the mpu by setting the temp_start (i/o ram 0x 28b4 [6]) control bit. in slp and lcd modes, it is awakened at a regular rate set by temp_per[2:0] (i/o ram 0x28a0[2:0]) . the result of the temperature measurement is read from the two i/o ram locations stemp[10:3] ( i/o ram 0x2881) a nd stemp[2:0] (i/o ram 0x2882[7:5] ). note that both of these i/o ram locations must be downloaded from: http:///
71m6543f/71m6543g data sheet 54 v2 read and properly combined to form the stemp[10:0] 11 - bit value (see stemp in table 45 ) . the resulting 11 - bit value is in 2s complement form and ranges from - 1024 to +1023 ( decimal ). the equation s below are used to calculate the sensed temperature. the first equation applies when the 71m6543f and 71m6543g are in msn mode and temp_pwr = 1. the second equation applies when the 71m6543f and 71m6543g are in brn mode , and in this case, the temp_pwr and temp_bsel bits m ust both be set to the same value, so that the battery that supplies the temperature sensor is also the battery that is measured and reported in bsense . thus, the second equation requires reading stemp and bsense . in the second equation, bsense (the sensed battery voltage) is used to obtain a more accurate temperature reading when the ic is in brn mode . the coefficients provided in the various stemp equations below are typical. for the 71m6543f and 71m6543g in msn mode (with temp_pwr = 1): 22 325 .0 ) ( + ? = stemp c temp for the 71m6543f and 71m6543g in brn mode, (with temp_p wr = temp_bsel ): 4.64 609 .0 00218 .0 325 .0 ) ( 2 + ? ? ? + ? = bsense bsense stemp c temp o table 45 s hows the i/o ram registers used for temperature and battery measurement. downloaded from: http:///
71m6543f/71m6543g data sheet v2 55 i f temp_pwr selects vbat_rtc when the battery is nearly discharged, the temperature measurement may not finish. in this case, firmware may complete the measurement by selecting v3p3d ( temp_pwr = 1). table 45 : i/o ram registers for temperature and battery measurement name location rst wk dir description tbyte_busy 28a0[3] 0 0 r indicates that hardware is still writing the 0x28a0 byte. additional writes to this byte are locked out while it is one. write duration could be as long as 6 ms. temp_per[2:0] 28a0[2:0] 0 C r/w sets the period between temperature measurements . auto mat ic measurements can be enabled in any mode (msn, brn, lcd, or slp). temp_per time 0 manual updates (see temp_start ) 1-6 2 ^ (3+ temp_per ) (seconds) 7 continuous temp_bat 28a0[4] 0 C r/w causes vbat to be measured whenever a temperature measurement is performed. temp_start 28b4[6] 0 C r/w temp_per[2:0] must be zero in order for temp_start to function. if temp_per[2:0] = 0, then setting temp_start s tarts a temperature measurement. ignored in slp and lcd modes. hardware clears temp_start when the temperature measurement is complete. temp_pwr 28a0[ 6] 0 C r/w selects the power source for the temp erature sensor: 1 = v3p3d, 0 = vbat_r tc. this bit is ignored in slp and lcd modes, where the temperature sensor is always powered by vbat_rtc. temp_bsel 28a0[7 ] 0 C r/w selects which battery is monitored by the temperature sensor: 1 = vbat, 0 = vbat_rtc temp_test[1:0] 2500[1:0] 0 C r/w test bits for the temperature monitor vco. temp_test must be 00 in regular operation. any other value cause s the vco to run continuously with the control voltage described below. temp_test function 00 normal operation 01 reserved for factory test 1x reserved for factory test stemp[10:3] stemp[2:0] 2881[7:0] 2882[7:5] r r the result of the temperature measurement. the stemp[10:0] value may b e obtained in c with a single 16 - bit read and divide by 32 operation as follows: volatile int16_t xdata stemp _at_0x2881; fa = (float)(stemp/32); bsense[7:0] 2885[7:0] C C r the result of the battery measurement. bcurr 2704[3] 0 0 r/w connects a 100 a load to the battery selected by temp_bsel . downloaded from: http:///
71m6543f/71m6543g data sheet 56 v2 2.5.6 71m6xx3 temperature sensor the 71m6xx3 includes an on - chip temperature sensor for determining the temperature of its bandgap re ference. the primary use of the temperature data is to determine the magnitude of compensation re - quired to offset the thermal drift in the system for the com pensation of the current measurement performed by the71m6xx3. see the 71m6xxx data sheet for the equation to calculate temperature from the 71m6xx3 stemp[10:0] reading. also, s ee 4.5 metrology temperature compensation on page 88 . see 2.2.8.3 control of the 71m6xx3 isolated sensor on page 22 for information on how to read the stemp[10:0] information from the 71m6xx3. 2.5.7 71m6543 battery monitor the 71m6543 temperature measurement circuit ca n also monitor the batteries at the vbat and vbat_rtc pins. t he battery to be tested (i.e., vbat or vbat_rtc pin ) is selected by temp_bsel ( i/o ram 0x28a0[7] ) . when temp_bat ( i/o ram 0x28a0[4] ) is set, a battery measurement is performed as part of each temperature measurement. the value of the battery reading is stored in regis ter bsense [7:0] (i/o ram 0x2885) . the following equation s are used to calculate the voltage measured on the vbat pin (or vbat_rtc pin) from the bsense[7:0] and stemp[10:0] values. the result of the equation below is in volts. a slightly different equation is used for msn mode and brn mode, as fol lows. in msn mode, temp_pwr = 1 use: v stemp v bsense v rtc orvbat vbat 000297 .0 0246 .0) 142 ( 3.3 ) _ ( ? + ? ? + = in brn mode, temp_pwr = temp_bsel use: v stemp v bsense v rtc orvbat vbat 000328 .0 0255 .0) 142 ( 291 .3 ) _ ( ? + ? ? + = in msn mode, a 100 a de - passivation load can be applied to the selected battery ( i.e. , selected by the temp_bsel bit) by setting the bcurr ( i/o ram 0x2704[3] ) bit. battery impedance can be measured by taking a battery measurement with and without bcurr . regardless of the bcurr bit setting, the battery load is never applied in brn, lcd, and slp modes. 2.5.8 71m6xx3 vcc monitor the 71m6xx3 monitor s its vcc pin voltage. the voltage of the vcc pin can be obtained by the 71m6543 by issuing a read command to the 71m 6xx3. the 71m6543 must request both the vsense[7:0] and stemp[10:0] values from the 71m6xx3. see the 71m6xxx data sheet for the equation to calculate the 71m6xx3 vcc pin voltage from the vsense[7:0] and stemp[10:0] values read from the 71m6xx3. see 2.2.8.3 control of the 71m6xx3 isolated sensor on page 22 for information on how to read vsense[7:0] and stemp[10:0] from the 71m6xx3 remote sensors. 2.5.9 uart and optical interface the 71m6543 provides two asynchronous interfaces, uart0 and uart1. both can be used to connect to amr modules, user interfaces, etc., and also support a mechanism for programming the on - chip flash memory. referring to figure 14 , uart1 includes an interface to implement an ir/optical port. the pin opt_tx is designed to directly drive an external led for transmitting data on an optical link. the pin opt_rx has the same threshold as the rx pin, but can also be used to sense the input from an ext ernal photo detector used as the receiver for the optical link. opt_tx and opt_rx are connected to a dedicated uart port (uart1). the opt_tx and opt_rx pins can be inverted with configuration bits opt_txinv (i/o ram 0x2456[0]) and opt_rxinv (i/o ram 0x2457[1]) , respectively. additionally, the opt_tx output may be modulated at 38 khz. modulation is available in msn and brn modes ( see table 61 ). the opt_txmod bit ( i/o ram 0x2456[1] ) enables modulation. the duty cycle is controlled by opt_fdc[1:0] (i/o ram 0x2457[5:4]) , which can select 50%, 25%, 12.5%, and 6.25% duty cycle. a 6.25% duty cycl e means that opt_tx is low for 6.25% of the period. downloaded from: http:///
71m6543f/71m6543g data sheet v2 57 when not needed for uart 1 , opt_tx can alternatively be configured as segdio51. configuration is via the opt_txe[1:0] (i/o ram 0x2456[3:2]) field and lcd_map[51] (i/o r am 0x2405[0]) . the opt_txe[1:0] field allows the mpu to select vpulse, wpulse, segdio51 or the out put of the pulse modulator to be sourced onto the opt_tx pin. likewise , the opt_rx pin can alternately be configured as segdio55, and i ts control is opt_rxdi s (i/o ram 0x2457[2]) and lcd_map[55] (i/o ram 0x2405[4]) . b a opt_txmod = 0 opt_txmod = 1, opt_fdc = 2 (25%) b a 1/ 38 khz opt_txinv from opt_tx uart mod en duty opt_tx opt_txmod opt_fdc opt_txe[1:0] 0 2 v3p3 internal a b 1 2 3 dio2 wpulse varpulse figure 14 : optical interface bit banged optical uart (third uart) as shown in figure 15 , the 71m654 3 can also be configured to drive the optical uart with a dio signal in a bit banged configuration. when control bit opt_bb ( i/o ram 0x2022[0] ) is set, the optical port is driven by dio5 and the segdio5 pin is driven by uart1_tx. this configuration is typically used when the two dedicated uarts must be connected to high speed clients and a slower optical uart is permissible. opt_txinv uart1_tx mod en duty segdio51/opt_tx opt_txmod opt_fdc opt_txe[1:0] 0 2 v3p3 internal a b opt_txmod =0 opt_txmod =1, opt_fdc =2 (25%) b a 1/38khz 1 2 3 dio51 wpulse varpulse seg51 lcd_map[51] 10 segdio55/opt_rx seg55 lcd_map[55] 10 dio55 10 opt_rxdis uart1_rx dio5 segdio5/tx2 seg5 10 lcd_map[5] opt_bb 0 0 11 figure 15 : optical interface (uart1) 2.5.10 digital i/o and lcd segment drivers 2.5.10.1 general information the 71m6543 combines most dio pins with lcd segment drivers. each seg /dio pin can be configured as a dio pin or as a segment driver pin (seg) . on reset or power - up, all dio pins are dio inputs (except for segdio0 - 15, see caution note below) until they are configured as desired under mpu control. the pin function can be conf igured by the i/o ram downloaded from: http:///
71m6543f/71m6543g data sheet 58 v2 registers lcd_mapn (0x2405 C 0x240b) . setting the bit corresponding to the pin in lcd_mapn to 1 configures the pin for lcd, setting lcd_mapn to 0 configures it for dio. after reset or power up, pins segdio0 through seg dio15 are initially dio outputs, but are disabled by port_e = 0 (i/o ram 0x270c[5] ) to avoid unwanted pulses during reset. after configuring pins segdio0 through segdio15 the mpu must enable these pins by setting port_e . once a pin is configured as dio, it can be configured independently as an input or output. for segdio 0 to segdio 15, this is done with the sfr registers p0 (sfr 0x80) , p1 (sfr 0x90) , p2 (sfr 0xa0) and p3 (sfr 0xb0) , as shown in table 47 . example: segdio12 (pin 32 in table 47 ) is configured as a dio output pin with a value of 1 (high) by writing 0 to bit 4 of lcd_map[15:8] , and writing 1 to both p3[4]and p3[0] . the same pin is con figured as an lcd driver by writing 1 to bit 4 of lcd_map[ 15:8 ] . the display information is written to bits 0 to 5 of lcd_seg12. the pb pin is a dedicated digital input and is not part of the segdio system. the ce features pulse counting registers and each pulse counter interrupt out put is internally routed to the pulse interrupt logic. thus, no routing of pulse signals to exter nal pins is required in order to generate pulse interrupts. see interrupt source n o. 2 in figure 12 . a 3 - bit configuration word, i/o ram register dio_rn ( i/o ram 0x2009[2:0] through 0x200e[6:4] ) can be used for pins segdio2 through segdio11 (when configured as dio) and pb to individually assign an internal resource such as an interrupt or a timer control ( dio_rpb [2:0], i/o ram 0x2450[2:0], configures the pb pin). this way, dio pins can be tracked even if they are configured as outp uts. table 47 lists t he internal resources which can be assigned using dio_r2[2:0] through dio_r11[2:0] and dio_rpb[2:0] . if more than one input is connected to the same resource, the resources are com bined using a logical or. table 46 : selectable resources using the dio_rn [2:0] bits value in dio_rn [2:0] resource selected for segdion or pb pin 0 none 1 reserved 2 t0 (counter0 clock) 3 t1 (counter1 clock) 4 high priority i/o interrupt (int0) 5 low priority i/o interrupt (int1) note: resources are selectable only on segdio2 through segdio11 and the pb pin. see table 48 . when driving leds, relay coils etc., the dio pins should sink the current into gndd (as shown in figure 16 , right), not source it from v3p3d (as shown in figure 16 , left). this is due to the resistance of the internal switch that connects v3p3d to either v3p 3sys or vbat. see 6.4.6 v3p3d switch on page 136 . sourcing current in or out of dio pins other than those dedicated for wake functions, for ex ample with pullup or pulldown resistors, must be avoided. violating this rule leads to increased quiescent current in sleep and lcd modes. downloaded from: http:///
71m6543f/71m6543g data sheet v2 59 figure 16 : connecting an external load to dio pins 2.5.10.2 combined dio and seg pins a total of 51 combined dio/lcd pins are available. these pins can be categori zed as follows: 39 combined dio/lcd segment pins : o segdio4segdio25 (22 pins) o segdio28segdio35 (8 pins) o segdio40segdio45 (6 pins) o segdio52segdio54 (3 pins) 12 combined dio/lcd segment pins shared with other functions: o segdio0/wpulse, segdio1/vpulse (2 pins) o segdio2/sdck, segdio3/sdata (2 pins) o segdio26/com5, segdio27/com4 (2 pins) o segdio36/spi_cszsegdio39/spi_cki (4 pins) o segdio51/opt_tx, segdio55/opt_rx (2 pins) additionally, 5 lcd segment (seg) pins are available. these pins can be categorized as follows: o 3 seg pins combined with the ice interface (seg48/e_rxtx, seg49/e_tclk, seg50/e_rst) o 2 seg pins combined with the test multiplexer outputs (seg46/tmux2out, seg 47/tmuxout) thus, a total of 51 dio pins are available with minimum lcd configuration, and a total of 56 lcd pins are available with minimum dio configuration. v3p3sys vbat v3p3d dio gndd mission brownout lcd/sleep low high high-z v3p3sys vbat v3p3d dio gndd mission brownout lcd/sleep low high high-z not recommended recommended downloaded from: http:///
71m6543f/71m6543g data sheet 60 v2 table 47 : data/direction registers and internal resources for seg dio 0 to segdio15 seg dio 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pin # 45 44 43 42 41 39 38 37 36 35 34 33 32 31 30 29 configuration : 0 = dio , 1 = lcd 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 lcd_map[7:0] (i/o ram 0x240b) lcd_map[15:8] (i/o ram 0x240a) seg data register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 lcd_seg0[5:0] to lcd_seg15[5:0] (i/o ram 0x2410[5:0] to 0x241f[5:0] dio data register 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 p0 ( sfr80 ) p1 (sfr 0x90) p2 ( sfr 0xa0 ) p3 ( sfr 0xb0 ) direction re gister : 0 = input, 1 = output 4 5 6 7 4 5 6 7 4 5 6 7 4 5 6 7 p0 ( sfr 0x80 ) p1 ( sfr 0x 90 ) p2 ( sfr 0xa0 ) p3 ( sfr 0xb0 ) internal re sources configurable (see table 46 ) C C y y y y y y y y y y C C C C the configuration for pins segdio 16 to segdio 31 is shown in table 48 , and the configuration for pins segdio 32 to segdio 45 is shown in table 49 . the configuration for pins segdio 51 to segdio 55 is shown in table 50 . table 48 : data/direction registers for segdi o16 to segdio31 seg dio 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 pin # 28 27 25 24 23 22 21 20 19 18 17 16 11 10 9 8 configuration: 0 = dio, 1 = lcd 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 lcd_map[23:16] (i/o ram 0x2409) lcd_map[31:24] (i/o ram 0x2408) seg data register 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lcd_segdio16[5:0] to lcd_segdio31[5:0] (i/o ram 0x2420[5:0] to 0x242f[5:0]) dio data register 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lcd_segdio16[0 ] to lcd_segdio31[0] (i/o ram 0x2420[0] to 0x242f[0]) direction re gister : 0 = input, 1 = output 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lcd_segdio16[1] to lcd_segdio31[1] (i/o ram 0x2420[1] to 0x242f[1]) table 49 : data/direction registers for segdio32 to segdio45 segdio 32 33 34 35 36 37 38 39 40 41 42 43 44 45 pin # 7 6 5 4 3 2 1 100 99 98 97 96 95 94 configuration: 0 = dio, 1 = lcd 0 1 2 3 4 5 6 7 0 1 2 3 4 5 lcd_map[39:32] (i/o ram 0x2407) lcd_map[45:40] (i/o ram 0x2406[5:0]) seg data register 32 33 34 35 36 37 38 39 40 41 42 43 44 45 lcd_segdio32[5:0] to lcd_segdio45[5:0] (i/o ram 0x2430[5:0] to 0x243d[5:0]) dio data register 32 33 34 35 36 37 38 39 40 41 42 43 44 45 lcd_segdio32[0] to lcd_segdio45[0] (i/o ram 0x2430[0] to 0x243d[0]) direction re gister: 0 = input, 1 = output 32 33 34 35 36 37 38 39 40 41 42 43 44 45 lcd_segdio32[1] to lcd_segdio45[1] (i/o ram 0x2430[1] to 0x243d[1]) downloaded from: http:///
71m6543f/71m6543g data sheet v2 61 table 50 : data/direction registers for segdio51 to segdio55 segdio 51 52 53 54 55 pin # 53 52 51 47 46 C C C configuration: 0 = dio, 1 = lcd 3 4 5 6 7 C C C lcd_map[55:48] (i/o ram 0x2405) seg data register 51 52 53 54 55 C C C lcd_segdio51[5:0] to lcd_segdio55[5:0] (i/o ram 0x2443[5:0] to 0x2447[5:0]) dio data register 51 52 53 54 55 C C C lcd_segdio51[0] to lcd_segdio55[0] (i/o ram 0x2443[0] to 0x2447[0]) direction re gister: 0 = input, 1 = output 51 52 53 54 55 C C C lcd_segdio51[1] to lcd_segdio55[1] (i/o ram 0x2443[1] to 0x2447[1]) 2.5.10.3 lcd drivers the lcd drivers are grouped into up to six co mmons (com0 C com5) and up to 56 segment drivers . the lcd interface is flexible and can drive 7 - segment digits, 14 - segment digits or enunciator symbols. a voltage doubler and a contrast dac generate vlcd from either vbat or v3p3sys, depending on the v3p3sys voltage. the voltage doubler, while capable of driving into a 500 k load , is able to generate a maximum lcd voltage that is within 1 v of twice the supply voltage . the doubler and d ac operate from a trimmed low - power reference . t he configuration of the vlcd generation is controlled by the i/o ram field lcd_vmode[1:0] (i/o ram 0x2401[7:6]) . it is decoded into lcd_ext, ldac_e, and lcd_bste . table 51 details the lcd_ v mode[1:0] configurations. table 51 : lcd_vmode configurations lcd_vmode [1:0] lcd_ext ldac_e lcd_bste description 11 1 0 0 external vlcd connected to the vlcd pin . 10 0 1 1 lcd boost is enabled. maximum vlcd voltage is 2*v3p3l - 1. vlcd = max(2*v3p3l - 1, 2. 6 5(1+ lcd_dac[4:0] /31) 01 0 1 0 lcd boost is disabled. the maximum vlcd voltage is v3p3l. vlcd = max(v3p3l, 2. 65 (1+ lcd_dac[4:0] /31) 00 0 0 0 vlcd=v3p3l, the lcd dac and lcd boost are dis - abled. in lcd mode, this setting causes the lowest battery current. note s: 1. lcd_ext, ldac_e and lcd_bste are 71m6543 internal signals which are decoded from the lcd_vmode[1:0] control field setting ( i/o ram 0x2401[7:6] ). each of these decoded signals, when asserted, has the effect indicated in the description column above, and as sum marized below. lcd_ext : when set, the vlcd pin expects an external supply voltag e ldac_e : whe n set, lcd dac is enabled lcd_bste : when set, the lcd boost circuit is enabled 2. v3p3l is an internal supply rail that is supplied from either the vbat pin or the v3p3sys pin , depending on the v3p3sys pin voltage. when the v3p3sys pin drops below 3.0 vdc, the 71m6543 switches to brn mode and v3p3l is source d from the vbat pin, otherwise v3p3l is sourced from the v3p3sys pin while in msn mode. downloaded from: http:///
71m6543f/71m6543g data sheet 62 v2 when using the vlcd boost circuit, use care when setting the lcd_dac[4:0] (i/o ram 0x240d[4:0]) value to ensure that the lcd manufacturers recommended operating voltage specif ication is not exceeded. the voltage doubler is active in all lcd modes including the lcd mode when lcd_bste = 1 . current dissipation in lcd mode can be reduced if the boost circuit is disabled and the lcd system is operated directly from vbat. the lcd dac uses a low - power reference and, within the constraints of vbat and the volta ge doubler, generate s a vlcd voltage of 2. 65 vdc + 2. 6 5 * lcd_dac[4:0] /3 1. two fuse bytes increase the accuracy of the lcd_dac. lcdadj12 and lcdadj0 indicate the actual vlcd output v oltage when the dac is programmed to 12 and 0 respectively. the lcd_bat (i/o ram 0x2402[7]) bit causes the lcd system to use the battery voltage in all power modes . this may be use ful when an external supply is available for the lcd system. t he advantage of connecting the external supply to vbat, rather than vlcd is that th e lcd dac is still active. if lcd_ext = 1, the vlcd pin must be driven from an external source. in this case, the lcd dac ha s no effect. the lcd system ha s the ability to drive up to six segments per seg driver. if the display is configured with six back planes, the 6 - way multiplexing reduces the number of seg pins required to drive a display and therefore enhance s the number of dio pins available to the application. refer to the lcd_mode[2:0] field (i/o ram 0x2400[6:4]) settings ( table 52 ) for the different lcd multiplexing choices. if 5 - state multiplexing is selected, segdio27 is converted to com4. if 6 - state multiplexing is s elected, segdio26 is converted to com5. these conversions override the seg/dio mapping of segdio26 and segd io27. additionally, independent of lcd_mode[2:0], if lcd_allcom = 1 ( i/o ram 0x2400[3]) , then segdio26 and segdio27 become com4 and com5 if their lcd_map [ ] bits are set. the lcd_on ( i/o ram 0x240c[0 ]) and lcd_blank ( i/o ram 0x240c[1] ) bits are an easy way to either blank the lcd display or turn it fully on. neither bit aff ect s the contents of the lcd data stored in the lcdseg_dio[ ] registers . in comparison, lcd_rst ( i/o ram 0x240c[2] ) clears all lcd data to zero. lcd_rst affects only pins that are configured as lcd . a small amount of power can be saved by programming the lcd frequency to the lo west value that provides satisfactory lcd visibility over the required temperature range. table 52 shows all i/o ram registers that control the operation of the lcd i nterface. downloaded from: http:///
71m6543f/71m6543g data sheet v2 63 table 52 : lcd configurations name location rst wk dir description lcd_allcom 2400[3] 0 C r/w configures all 6 seg/com pins as com. has no effect on pins whose lcd_map bit is zero. lcd_bat 2402[7] 0 C r/w connects the lcd power supply to vbat in all mod es. lcd_e 2400[7] 0 C r/w enables the lcd display. when disabled, vlc2, vlc1, and vlc0 are ground as are the com and seg outputs if their lcd_map bit is 1. lcd_on lcd_blank 240c[0] 240c[1] 0 0 C C r/w r/w lcd_on = 1 turns on all lcd segments without affecting the lcd data. similarly, lcd_blank = 1 turns off all lcd segments without affecting the lcd data. if both bits are set, all lcd segments are turned on . lcd_rst 240c[2] 0 C r/w clear all bits of lcd data. these bits affect segdio pins that are configured as lcd drivers. lcd_dac[4:0] 240d[4:0] 0 C r/w th is register controls the lcd contrast dac which adjust s the vlcd voltage and has an output range of 2. 65 vdc to 5 .3 vdc . the vlcd voltage is vlcd = 2. 6 5 + 2. 6 5 * lcd_dac[4:0] /3 1 thus, the lsb of the dac is 85.5 mv. the maximum dac output voltage is limited by v3p3 sys, vbat, and whether lcd_bste is set . lcd_clk[1:0] 2400[1:0] 0 C r/w sets the lcd clock frequency (1/t). see definition of t in figure 17 . note: fw = 32768 hz 00 - fw/2^9, 01 - fw/2^8, 10 - fw/2^7, 11 - fw/2^6 lcd_mode[2:0] 2400[6:4] 0 C r/w the lcd bias and multiplex mode. lcd_mode output 000 4 states, 1/3 bias 001 3 states, 1/3 bias 010 2 states, ? bias 011 3 states, ? bias 100 static display 101 5 states, 1/3 bias 110 6 states, 1/3 bias lcd_vmode[1:0] 2401[7:6] 00 00 r/w this register specifies how vlcd is generated. lcd_vmode description 11 external vlcd 10 lcd boost and lcd dac enabled 01 lcd dac enabled 00 no boost and no dac. vlcd = vbat or v3p3sys t he lcd can be driven in static, ? bias, and 1/3 bias modes. figure 17 defines the com waveforms. note that com pins that are not require d in a specific mode maintain a segment off state rather tha n gnd, vcc, or high impedance . the segment driver s segdio 22 and segdio23 can be configured to blink at either 0.5 hz or 1 hz. the blink rate is con trolled by lcd_y (i/o ram 0x2400[2]) . there can be up to six pixels/segments connected to each of these driver pin s . the i/o ram fields lcd_blkmap 22 [5 :0] (i/o ram 0x2 402[5:0]) and lcd_blkmap 23 [5 :0] (i/o ram 0x2401[5:0]) i dentif y which pixels, if any, are to blink. lcd_blkmap22[5:0] and lcd_blkmap23[5:0] are non - volatile. downloaded from: http:///
71m6543f/71m6543g data sheet 64 v2 the lcd bias may be compensated for temperature using the lcd_dac [4:0] field ( i/o ram 0x240d[4:0 ] ). the bias may be adjusted from 1.4 v below the 3.3 v supply (v3p3sys in msn mode and vbat in brn and lcd mode s ). when the lcd_dac[4:0] field is set to 000, the dac is bypassed and powered down. this setting can be used to reduce current in lcd mode. figure 17 : lcd w aveforms seg46 through seg50 cannot be configured as dio pins. display data for these pins are written to i/o ram registers lcd_seg46[5:0] through lcd_seg50[5:0] (see table 53 ) . table 53 : lcd data registers for segdio46 to segdio5 5 seg dio 46 47 48 49 50 51 52 53 54 55 pin # 93 92 58 57 56 53 52 51 47 46 configuration : always lcd pins see 2.5.10.2 seg data register lcd_segdio46[5:0] (i/o ram 0x243e[5:0] lcd_segdio47[5:0] (i/o ram 0x243f[5:0]) lcd_segdio48[5:0] (i/o ram 0x2440[5:0] lcd_segdio49[5:0] (i/o ram 0x2441[5:0]) lcd_segdio50[5:0] (i/o ram 0x2442[5:0]) lcd_segdio51[5:0] (i/o ram 0x2443[5:0]) lcd_segdio52[5:0] (i/o ram 0x2444[5:0]) lcd_segdio53[5:0] (i/o ram 0x2445[5:0]) lcd_segdio54[5:0] (i/o ram 0x2446[5:0]) lcd_segdio55[5:0] (i/o ram 0x2447[5:0]) the lcd_map[ 47 :46] ( i/o ram 0x2406[7:6] ) bits are used to determine whether seg46 and seg 47 are seg pins or their alternate function (see pins 93 and 92 in figure 42 ). if the lcd_map[ 4 7:46 ] bit s are 1 , then the pin s are configured as seg pin s . if the lcd_map[ 4 7:46 ] bit s are 0, then the pin s are configured as their alternate functions (tmux2out and tm uxout , respectively ). static (lcd_mode=100) com0 com1 com2 com3 com4 com5 seg_on seg_off (1/2) (1/2) (1/2) (1/2) (1/2) 1/2 bias, 2 states (lcd_mode = 010 ) com0 com1 com2 com3 com4 com5 seg_on seg_off (1/2) (1/2) (1/2) (1/2) 0 1 1/2 bias, 3 states (lcd_mode = 011 ) com0 com1 com2 com3 com4 com5 seg_on seg_off (1/2) (1/2) (1/2) 0 1 2 1/3 bias, 3 states (lcd_mode = 011 ) com0 com1 com2 com3 com4 com5 seg_on seg_off (2/3) 0 1 2 (1/3) 1/3 bias, 4 states (lcd_mode = 000 ) com0 com1 com2 com3 com4 com5 seg_on seg_off 0 1 2 1/3 bias, 6 states (lcd_mode = 110 ) com0 com1 com2 com3 com4 com5 seg_on seg_off 0 1 2 3 3 4 5 t downloaded from: http:///
71m6543f/71m6543g data sheet v2 65 for example, if lcd_map[46] = 1, then pin 93 (tmux2out/seg46) is configured as seg46, and if lcd_map[46]=0 , then pin 93 is configured as tmux2out. the seg pins with alternate ice interface function ( see pins 56 - 58 in figure 42 ) are forced to their alternate ice interface function ( i.e., e_rxtx, e_tclk and e_rst) if the ice_e pin (pin 59) is driven high, and in this ca se, the bits lcd_map[50 :48 ] ( i/o ram 0x2405[2:0] ) bit s are dont care bits . if the ice_e pin i s driven low, then lcd_map[50 :48 ] bits m ust written with 1 in order to configure these pins as seg pin s . if the ice_e pin is low and lcd_map[50:48 ] are written with 0, then these pins are tied to an internal pullup . 2.5.11 eeprom interface the 71m6543 provides hardware support for either a two - pin or a three - wire ( - wire) type of eeprom interfa ce. the interfaces use the eectrl (sfr 0x9f) and eedata (sfr 0x9e) registers for communication . 2.5.11.1 two -p in eeprom interface the dedicated 2 - pin serial interface communicates with external eeprom devices . the interface is mul tiplexed onto the segdio2 ( sdck ) and segdio3 ( sdata ) pins and is selected by setting dio_eex [1:0] = 01 ( i/o ram 0x2456[7:6] ). the mpu communicates with the interface through the sfr registers eedata and eectrl . if the mpu wishes to write a byte of data to the eeprom, it places the data in eedata and then writes the transmit code to eectrl . this initiates the transmit operation which is finished when the busy bit falls . int5 is also asserted when busy falls . the mpu can then check the rx_ack bit to see if the eeprom acknowledged the trans mission. a byte is read by writing the receive command to eectrl and waiting for the busy bit to fall . upon completion, the received data is in eedata . the serial transmit and receive clock is 78 khz during each transmission, and then holds in a high state until the next trans mission . the eectrl bits wh en the two - pin interface is selected are shown in table 54 . table 54 : eectrl bits for 2 - pin interface status bit name read/ write reset state polarity description 7 error r 0 positive 1 when an illegal command is received. 6 busy r 0 positive 1 when serial data bus is busy. 5 rx_ack r 1 positive 1 indicates that the eeprom sent an ack bit. 4 tx_ack r 1 positive 1 indicates when an ack bit has been sent to the eeprom . 3:0 cmd[3:0] w 0000 positive cmd[3:0] operation 0000 no - op command. stops the i 2 c clock ( sdck ). if not issued, sdck keeps toggling. 0010 receive a byte from the eeprom and send ack. 0011 transmit a byte to the eeprom. 0101 issue a stop sequence. 0110 receive the last byte from the eeprom and do not send ack. 1001 issue a start sequence. others no operation, set the error bit. the eeprom interface can also be operated by controlling the dio 2 and dio 3 pins directly. the direction of the dio line can be changed from input to output and an output value can be written with a single write operation, thus avoiding collisions (see table 14 port registers (segdio0 - 15) ). therefore, no resistor is required in series sdata to protect against coll isions. downloaded from: http:///
71m6543f/71m6543g data sheet 66 v2 2.5.11.2 three -w ire ( - wire) eeprom interface with single data pin a 500 khz three - wire interface, using sdata, sdck , and a dio pin for cs is available . the interface is selected by setting dio_eex [1:0] = 10 . the eectrl bits when the three - wire interface is selected are shown in table 55 . when eectrl is written, up to 8 bits from eedata are either written to the eeprom or read from the eeprom, depending on the values of the eectrl bits. 2.5.11.3 three -w ire ( - wire/spi ) eeprom interface with separate di/do pins if dio_eex[1:0] = 11 , the 71m6543 three - wire interface is the same as above, except di and do are separate pins. in this case, segdio3 becomes do and segdio 8 becomes di. the timing diagrams are the same as for dio_eex [1:0] = 10 except that all output data appears on do and all input data is expected on di. in this mode, di is ignored while data is being received on do . this mode is compatible with spi modes 0,0 and 1,1 where data is shifted out on the falling edge of t he clock and is strobed in on the rising edge of the clock. table 55 : eectrl bits for the 3 -w ire interface control bit name read/ write description 7 wfr w wait for ready . if this bit is set, the trailing edge of busy is de layed until a rising edge is seen on the data line . this bit can be used during the last byte of a write command to cause the int5 interrupt to occur when the eeprom has finished its internal write sequence . this bit is ignored if hiz=0. 6 busy r asserted while the serial data bus is busy . when the busy bit falls, an int5 interrupt occurs. 5 hiz w indicates that the sd signal is to be floated to high impedance immedi ately after the last sdck rising edge. 4 rd w indicates that eedata ( sfr 0x9e ) is to be filled with data from eeprom. 3 :0 cnt[3:0] w specifies the number of clocks to be issued . allowed values are 0 through 8 . if rd = 1, cnt bits of data are read msb first, and right justified into the low order bits of eedata . if rd = 0, cnt bits are sent msb first to the eeprom, shifted out of the msb of eedata . if cnt[3:0] is zero, sdata simply obey s the hiz bit . the timing diagrams in figure 18 through figure 22 describe the 3 - wire eeprom interface behavior . all commands begin when the eectrl register is written . transactions start by first raising the dio pin that is connected to cs . multiple 8 - bit or less commands such as those shown in figure 18 through figure 22 are then sent via eectrl and eedata . when the transaction is finished, cs must be lowered . at the end of a read transaction, the eeprom driv es sdata, but transition s to hiz (high impedance) when cs falls . the firmware should then immediately issue a write command with cnt=0 and hiz=0 to take control of sd ata and force it to a low - z state. figure 18 : 3 -w ire interface . write command, hiz=0. sclk (output) busy (bit) cnt cycles (6 shown) sdata (output) write -- no hiz d2 d3 d4 d5 d6 d7 eectrl byte written int5 sdata output z (loz) downloaded from: http:///
71m6543f/71m6543g data sheet v2 67 figure 19 : 3 -w ire interface . write command, hiz=1 figure 20 : 3 -w ire interface . read command. figure 21 : 3 - wire interface . write command when cnt=0 figure 22 : 3 -w ire interface . write command when hiz=1 and wfr=1. 2.5.12 spi slave port the slave spi port communicates directly with the mpu data bus and is abl e to read and write data ram and configuration ram (i/o ram) locations . it is also able to send commands to the mpu . the interface to the slave port consists of the sp i_ csz, sp i_c ki , s pi_ di and sp i_ do pins . these pins are multi plexed with the combined dio/lcd segment driver pins seg dio 36 to seg dio39 (pins 3, 2, 1 and 100) . additionally, the spi interface allows flash memory to be read and to be programmed. to facilitate flash programming, cycling power or asserting reset causes the spi port pins to default to spi mode. the spi port is disabled by clearing the spi_e bit (i/o ram 0x270c[4]) . possible applications for the spi interface are: cnt cycles (6 shown) write -- with hiz int5 eectrl byte written sclk (output) busy (bit) sdata (output) d2 d3 d4 d5 d6 d7 (hiz) (loz) sdata output z cnt cycles (8 shown) read d0 d1 d2 d3 d4 d5 int5 d6 d7 eectrl byte written sclk (output) busy (bit) sdata (input) sdata output z (hiz) cnt cycles (0 shown) write -- no hiz d7 int5 not issued cnt cycles (0 shown) write -- hiz int5 not issued eectrl byte written eectrl byte written sclk (output) busy (bit) sdata (output) sclk (output) busy (bit) sdata (output) (hiz) sdata output z sdata output z (loz) cnt cycles (6 shown) write -- with hiz and wfr eectrl byte written sclk (output) busy (bit) sdata (out/in) d2 d3 d4 d5 d6 d7 busy ready (from eeprom) int5 (from 6520) sdata output z (hiz) (loz) downloaded from: http:///
71m6543f/71m6543g data sheet 68 v2 1) an external host reads data from ce locations to obtain metering informat ion. this can be used in applications where the 71m6543 function as a smart front - end with preprocessing capability. since the addresses are in 16 - bit format , any type of xram data can be accessed: ce, mpu, i/o ram, but not sfrs or the 80515 - internal register bank. 2) a communication link can be established via the spi interface: by writing int o mpu memory locations, the external host can initiate and control processes in the 71m6543 mpu. w riting to a ce or mpu location normally generates an interrupt, a function that can be used to signal to the mpu that the byte that had just been written by the external host must be read and proc essed. data can also be inserted by the external host without generating an interrupt. 3) an external dsp can access front - end data generated by the adc. this mode of operation uses the 71m6543 as an analog front - end (afe). 4) flash programming by the external host (spi flash mode) . spi transactions a typical spi transaction is as follows. while spi_csz is high, the port is held in an initialized/reset state. during this state, spi_do is held in high impedance state and all transitions on spi_clk and spi_di are ignored. when spi_csz falls, the port begin s the transaction on the first rising edge of spi_clk. as shown in table 56 , a transaction consists of an optional 16 bit address, an 8 bit command, an 8 bit status byte, followed by one or more bytes of data. the transaction ends when spi_csz is raised. some transactions may consist of a command only. when spi_csz rises, spi command bytes that are not of the form x000000 0 cause the spi_cmd (sfr 0xfd) register to be updated and then cause an interrupt to be issued to the mpu. the exception is if the transaction was a single byte. in this case, the spi_cmd byte is always updated and the interrupt issued. spi_cmd is not cleared when spi_csz is high. the spi port supports data transfers up to 10 mb/s. a serial read or write operation requires at least 8 clocks per byte, guaranteeing spi access to the ram is no faster than 1.25 mhz, thus ensuring that spi access to dram is always possible. table 56 : spi transaction fields field name required size (bytes) description address yes, except single byte transaction 2 16 - bit address. the address field is not required if the transaction is a simple spi command . command yes 1 8- bit command . this byte can be used as a command to the mpu. in multi - byte transactions, the msb is the r/w bit. unless the transaction is multi - byte and spi_ cmd is exactly 0x80 or 0x00, the spi_cmd register is updated and an spi interrupt is issued. otherwise, the spi_cmd register is unchanged and the interrupt is not issued. s tatus yes, if transaction includes data 1 8- bit status field, indicating the status of the previous transaction. this byte is also available in the mpu memory map as spi_stat (i/o ram 0x2708) . see table 58 for the contents. d ata yes, if transaction includes data 1 or more the read or write data. address is auto incremented for each new byte. the spi_stat byte is output on every spi transaction and indicates the parity of the previ ous transaction and the error status of the previous transaction. potential error s ources are: ? 71m6543 not ready ? t ransaction not ending on a byte boundary. downloaded from: http:///
71m6543f/71m6543g data sheet v2 69 spi safe mode sometimes it is desirable to prevent the spi interface from writing to arbitrary ram locations and thus disturbing mpu and ce operation. this is especially true in afe applications. for this reason, the spi s afe mode was created. in spi safe mode , spi write operation s are disabled except for a 16 byte transfer region at address 0x 400 to 0x 40f. if the spi host needs to write to other addresses, it must use the spi_cmd register to request the write operation from the mpu . spi safe mode is enabled by t he spi_safe bit (i/o ram 0x270c[3]) . single - byte transaction if a transaction is a single byte, the byte is interpreted as spi _cmd. regardless of the byte value, single - byte transactions always update the spi_cmd register and cause an spi interrupt to be generated. multi - byte transaction as shown in figure 23 , multi - byte operations consist of a 16 bit address field, an 8 bit cmd, a status byte, and a sequence of data bytes. a multi byte transaction is three or more by tes. a15 a14 a1 a0 c0 0 31 x d6 d1 d0 d7 d6 d1 d0 c5 c6 c7 (from host) spi_csz (from host) spi_ck (from host) spi_di (from 6543) spi_do 8 bit cmd 16 bit address data[addr] data[addr+1] 15 16 23 24 32 39 extended read . . . serial read a15 a14 a1 a0 c0 c5 c6 c7 x 8 bit cmd 16 bit address data[addr] data[addr+1] extended write . . . serial write d6 d1 d0 d7 d6 d1 d0 x hi z hi z status byte st7 st6 st5 st0 d7 40 47 0 31 15 16 23 24 32 39 40 47 status byte d7 st7 st6 st5 st0 (from host) spi_csz (from host) spi_ck (from host) spi_di (from 6543) spi_do figure 23 : spi slave port - typical multi - byte r ead and w rite operations table 57 : spi c ommand sequence s c ommand sequence d escription addr 1xxx xxxx status byte0 ... byten read data starting at addr. addr is auto - incremented until spi_csz is raised. upon completion, spi_cmd ( sfr 0xfd ) is updated to 1xxx xxxx and an spi interrupt is generated. the exception is if the com mand byte is 1000 0000. in this case, no mpu interrupt is generated and spi_cmd is not updated. addr 0xxx xxxx status byte0 ... byten write data starting at addr. addr is auto - incremented until spi_csz is raised. upon completion, spi_cmd is updated to 0xxx xxxx and an spi interrupt is generated. the exception is if the command byte is 0000 0000. in this case, no mpu interrupt is generated and spi_cmd is not updated. table 58 : spi registers name location rst wk dir description ex_spi 2701[7] 0 0 r/w spi interrupt enable bit. spi_cmd sfr fd[7:0] C C r spi command. the 8 - bit command from the bus master. spi_e 270c[4] 1 1 r/w spi port enable bit. it enables the spi interface on pins segdio36 C segdio39. ie_spi sfr f8[7] 0 0 r/w spi interrupt flag. set by hardware, cleared by writing a 0. downloaded from: http:///
71m6543f/71m6543g data sheet 70 v2 name location rst wk dir description spi_safe 270c[3] 0 0 r/w limits spi writes to spi_cmd and a 16 byte region in dram when set. no other write operations are permitted. spi_stat 2708[7:0] 0 0 r spi_stat contains the status results from the previous spi transaction bit 7 - 71m6543 ready error: the 71m6543 was not ready to read or write as directed by the previous command. bit 6 - read data parity: this bit is the parity of all bytes read from the 71m6543 in the previous command. does not include the spi_stat byte. bit 5 - write data par ity: this bit is the overall parity of the bytes written to the 71m6543 in the previous command. i t includes cmd and addr bytes. bit 4 :2 - bottom 3 bits of the byte count. does not in clude addr and cmd bytes. one, two, and three byte instructions return 111. bit 1 - spi flash mode: this bit is zero when the test pin is zero. bit 0 - spi flash mode ready: used in spi flash mode. indicates that the flash is ready to receive another write instruction. spi flash mode (sfm) in normal operati on, the spi slave interface can not read or write the flash memory. however, the 71m6543 supports a special flash mode (sfm) which facilitates initial programming of the flash memory. when the 71m6543 is in this mode, the spi can erase, read, and write the flash memory . other memor y elements such as xram and io ram are not accessible in this mode. in order to protect the flash contents, several operations are required before the sfm mode is successfully invoked. in sfm mode, the 71m6543 supports n byte reads and dual - byte writes to flash memory . see the spi transaction description on page 68 for the format of read and write commands. since the flash write op eration is always based on a two - byte word, the initial address must always be even. data is written to the 16 - bit flas h memory bus after the odd word is written. when the 71m6543g is operating sfm, spi single - byte transactions are used to write to fl_bank[1:0] (sfr 0xb6[1:0]) . during an spi single - byte transaction, spi_cmd[1:0] will over - wr ite the contents of fl_bank[1:0] (sfr 0xb6[1:0]) . this will allow for access of the entire 128 kb flash memory w hile operating in sfm. in sfm mode, the mpu is completely halted. for this reason, the interrupt feature described in the spi transaction section above is not available in sfm mode. the 71m6543 must be reset by the wd timer or by the reset pin in order to exit sfm mode. invoking sfm the following conditions must be met prior to invoking sfm: ? ice_e = 1. this disables the watchdog and adds another layer of protection against inadvertent flash corruption. ? the external power source (v3p3sys, v3p3a) is at the proper level (> 3.0 vdc) . ? preboot = 0 ( sfr 0xb2[7]) . this validates the state of the secure bit (sfr 0xb2[6]) . ? secure = 0. this i/o ram register indicates that spi secure mode is not enabled. operations are limited to sfm mass erase mode if the secure bit = 1 (flash read back is not allowed in secure mode). ? flsh_unlock[3:0] = 0010 ( i/o ram 0x2702[7:4]) . downloaded from: http:///
71m6543f/71m6543g data sheet v2 71 the i/o ram r egisters sfmm ( i/o ram 0x2080 ) and sfms (i/o ram 0x2081) a re used to invoke sfm. only the spi interface has access to these two registers. this eliminates an indir ect path from the mpu for disabling the watchdog. sfmm and sfms need to be written to in sequence in order to invoke sfm. this sequential write process prevent s inadvertent entering of sfm. the sequence for invoking sfm is: ? first, write to sfmm ( i/o ram 0x2080 ) register . th e value written to this register defines the sfm mode. o 0xd1: mass erase mode. a flash mass erase cycle is invoked upon entering sfm. o 0x2e: flash read back mode. sfm is entered for flash read back purposes. flash writes will not be blocked and it is up to the user to guarantee that only previously unwritt en locations are written. this mode is not accessible when spi secure mode is set. o sfm is not invoked if any other pattern is written to th e sfmm register. ? next, write 0x 96 to the sfms ( i/o ram 0x2081 ) register . this write invoke s sfm provided that the previous write operation to sfmm met the requirements. writing any other pattern to this register does not invoke sfm. addi tionally, any write operations to this register automatically reset the previously written sfmm register values to zero. sfm d etails the following occur s upon entering sfm. ? the ce is disabled. ? the mpu is halted. once the mpu is halted it can only be restarted with a reset . this reset can be accomplished with the reset pin , a watchdog reset , or by cycling power (without battery at the vbat pin) . ? the flash control logic is reset in case the mpu was in the middle of a flash write operation or erase cycle. ? mass erase is invoked if specified in the sfmm ( i/o ram 0x2080 ) register (see invoking sfm, above) . the secure bit ( sfr 0xb2[6] ) is cleared at the end of this and all mass erase cycles. ? all spi read and write operation s now refer to flash instead of xram space. the spi host can access the current state of the pending multi - cycle flash access by performing a 4 - byte spi write of any address and checking the status field. all spi write operations in sfm mode must be 6 - byte write transaction s that write two bytes to an even address. the write transactions must contain a command byte of 0x00 which is t he form that does not create an mpu interrupt. auto incrementing is disabled for write operation s. spi read transactions can make use of auto increment and may access single bytes. the command byte must always be 0x80 in sfm read transactions. spi commands in sfm interrupts are not generated in sfm since the mpu is halted. the format of the co mmands is shown in the spi transactions description on page 68 . spi transactions 2.5.13 hardware watchdog timer a n independent, robust, fixed - duration, watchdog timer (wdt) is included in the 71m6543 . it u ses the rtc crystal oscillator as its time base and must be refreshed by t he mpu firmware at least every 1.5 seconds. when not refreshed on time, the wdt overflows and the part is r eset as if the reset pin were pulled high, except that the i/o ram bits are in the same state as after a wake - up from slp or lcd modes (see the i/o ram description in 5.2 for a list of i/o ram bit states after reset and wake - up). four thousand, one hundred ck32 cycles (or 125 ms) after the wdt overflow, the mpu is launched from program address 0x0000 . the watchdog timer is also reset when the internal signal wake=0 (see 3.4 wake - up behavior ). the wdt is disabled when the ice_e pin is pulled high. for details, see 3.3.4 watchdog timer (wdt) reset . downloaded from: http:///
71m6543f/71m6543g data sheet 72 v2 2.5.14 tes t ports (tmuxout and tmux2out p in s) two independent multiplexers allow the selection of internal analog and digital signals for the tmuxout and tmux2out pins. these pins are multiplexed with the seg47 and seg46 function. in order to function as test pins, lcd_map[46] ( i/o ram 0x2406[6]) and lcd_map[47] ( i/o ram 0x2406[7] ) must be 0. one of the digital or analog signals listed in table 60 can be selected to be output on the tmuxout pin . the function of the multiplexer is controlled with the i/o ram register tmux [4:0] (i/o ram 0x2502[4:0] , as shown in table 59 . one of the digital or analog signals listed in table 60 can be selected to be output on the tmux 2 out pin. the function of the multiplexer is controlled with the i/o ram reg ister tmux 2 [4:0] (i/o ram 0x2503[4:0]) , as shown in . the tmux and tmux2 i/o ram locations are non - volatile and their contents are preserved by battery power and across resets. the tmuxout and tmux2out pin s may be used for diagnosis purposes or in production test. the rtc 1 - second output may be used to calibrate the crystal oscillator. the rtc 4 - second output provides even higher precision. table 59 : tmu x[4 :0] selections tmux[5:0] signal name description 1 rtclk 32.768 khz clock waveform 9 wd_rst indicates when the mpu has reset the watchdog timer. can be monitored to determine spare time in the watchdog timer. a ckmpu mpu clock C see table 8 d v3aok bit indicates that the v3p3a pin voltage is 3.0 v. the v3p3a and v3p3sys pins are expected to be tied together at the pcb level. the 71m654 3 monitors the v3p3a pin voltage only. e v3ok bit indicates that the v3p3a pin voltage is 2.8 v. the v3p3a and v3p3sys pins are expected to be tied together at the pcb level. the 71m654 monitors the v3p3a pin voltage only. 1b mux_sync internal multiplexer frame sync signal. see figure 4 and figure 5 . 1c ce_busy interrupt see 2.3.3 on page 25 and figure 12 on page 45 1d ce_xfer interrupt 1f rtm output from ce see 2.3.5 on page 26 note: all tmux[5:0] values which are not shown are reserved. downloaded from: http:///
71m6543f/71m6543g data sheet v2 73 table 60 : tmux2[4:0] selections tmux2[4:0] signal name description 0 wd_ovf indicates when the watchdog timer has expired (overflowed). 1 pulse_1s one second pulse with 25% duty cycle. this signal can be used to measure the deviation of the rtc from an ideal 1 second interval. multiple cycles should be averaged together to filter out jitter. 2 pul se_4s four second pulse with 25% duty cycle. this signal can be used to measure the deviation of the rtc from an ideal 4 second interval. multiple cycles should be averaged together to filter out jitter. the 4 second pulse provides a more precise measureme nt than the 1 second pulse. 3 rtclk 32.768 khz clock waveform 8 spare[1] bit C i/o ram 0x2704[1] copies the value of the bit stored in 0x2704[1]. for general purpose use. 9 spare[2] bit C i/o ram 0x2704[2] copies the value of the bit stored in 0x2704[2]. for general purpose use. a wake indicates when a wake event has occurred. b mux_sync internal multiplexer frame sync signal. see figure 4 and figure 5 . c mck see 2.5.3 on page 49 . e gndd digital gnd. use this signal to make the tmux2out pin static. 12 int0 C dig i/o interrupt 0. see 2.4.8 on page 39 . also see figure 12 on page 45 . 13 int1 C dig i/o 14 int2 C ce_pulse 15 int3 C ce_busy 16 int4 - vstat 17 int5 C eeprom/spi 18 int6 C xfer, rtc 1f rtm_ck (flash) see 2.3.5 on page 26 . note: all tmux 2[4 :0] values which are not shown are reserved. downloaded from: http:///
71m6543f/71m6543g data sheet 74 v2 3 functional d escription 3.1 theory of operation the energy delivered by a power source into a load can be expressed as: = t dt tit v e 0 )( )( assuming phase angles are constant, the following formulae apply: ? p = real energy [wh] = v * a * cos * t ? q = reactive energy [varh] = v * a * sin * t ? s = apparent energy [vah] = 2 2 q p + for a practical meter, not only voltage and current amplitudes, but also phase angles and harmonic con tent may change constantly . thus, simple rms measurements are inherently inaccurate . a modern solid - state electricity meter ic such as the 71m6543 functions by emulating the integral oper ation above, i.e. it processes current and voltage samples through an adc at a cons tant frequency . as long as th e adc resolution is high enough and the sample frequency is beyond the harmonic range of interest, the current and voltage samples, multiplied with the time period of sampling yi eld s an accurate quantity for the momentary energy . summing - up the momentary energy quantities over time result s in accumulated energy. figure 24 : voltage , current, momentary and accumulated energy figure 24 shows the shapes of v(t), i(t), the momentary power and the accumulat ed power, resulting from 50 samples of the voltage and current signals over a period of 20 ms . the application of 240 vac and 100 a results in an accumulation of 480 ws (= 0.133 wh) over the 20 ms period, as indicated by the a ccumulated p ower curve . the described sampling method works reliably, even in the presence of dynam ic phase shift and harmonic distortion. 3.2 battery modes shortly after system power (v3p3sys) is applied, the 71m6543 is in miss ion mode (msn mode). msn mode means that the part is operating with system power and that the internal p ll is stable. this mode is the normal operating mode where the part is capable of measuring energy. -500 -400 -300 -200 -100 0 100 200 300 400 500 0 5 10 15 20 current [a] voltage [v] energy per interval [ws] accumulated energy [ws] downloaded from: http:///
71m6543f/71m6543g data sheet v2 75 when system power is not available, the 71m654 3 is in one of three battery modes: ? brn mode (brownout mode) ? lcd mode (lcd - only mode) ? slp mode (sleep mode) . an internal comparator monitors the voltage at the v3p3sys pin (note that v3p3sys and v3p3a are typically connected together at the pcb level). when the v3p3sys dc voltage drops below 2.8 vdc, the comparator resets an internal power status bit called v3ok . as soon as system power is removed and v3ok = 0 , the 71m654 3 is forced to brn mode. the mpu continues to execute code when the system transitions from msn to brn mode or from brn to msn mode. a soft res et should be executed when returning from brn to msn mode in order to re - initialize the i/o ram. depending on the mpu code, t he mpu can choose to stay in brn mode, or transition to lcd or to slp mode ( via the i/o ram bits lcd_only , i/o ram 0x28b2[6] and sleep, i/o ram 0x28b2[7] ) . brn mode is similar to msn mode except that resources powered by system power, such as the adc and the ce, are n ot available (see table 61 ) , and that the supply current is drawn from the vbat pin. in brn mode, t he pll continues to function at the same frequency as in msn mode. the mpu can configure brn mode as it desires . for instance, it may choose to minimize battery power by reducing the pll or mpu clock speed (see 3.2.1 brn mode , for the recommended settings to realize minimum power consumption in brn mode). when system power is restored, the 71m6543 automatically transition s from any of the battery modes (brn, lc d, slp) back to msn mode. figure 25 shows a state diagram of the various operatin g modes, with the possible transitions between modes . when the part wa kes - up under battery power, the part automatically enter s brn mode (see 3.4 wake - up behavior ). from brn mode, the part may enter either lcd mode or slp mode, as controlled by the mpu. figure 25 : operation modes state diagram v3p3sys rises v3p3sys falls msn brn lcd sleep or vbat insufficient system power battery power lcd_only reset & vbat sufficient reset wake flags wake event reset & vbat insufficient v3p3sys rises v3p3sys rises slp wake event vbat insufficient vbat insufficient vstat=001 vstat=00x downloaded from: http:///
71m6543f/71m6543g data sheet 76 v2 transitions from both lcd and slp mode to brn mode c a n b e initiated by the following events: ? w ake - up timer time out. ? p ushbutton (pb) is activated . ? a rising edge on segdio4, or a high logic level on segdio52 or segdio55. ? activity on the rx or opt_rx pins. the mpu has access to a variety of registers that signal the event that c aused the wake up. see 3.4 wake - up behavior for details. table 61 shows the circuit functions available in each operating mode. table 61 : available circuit functions circuit function system power battery power msn (mission mode) brn (brownout mode) lcd sleep pll_fast=1 pll_fast=0 pll_fast=1 pll_fast=0 ce (computation engine) yes yes -- 1 -- -- -- fir yes yes -- -- -- -- adc, vref yes yes -- -- -- -- pll yes yes yes yes b oost 2 -- battery measurement yes yes yes yes -- -- temperature sensor yes yes yes yes yes yes max mpu clock rate 4.92mhz (from pll) 1.57mhz (from pll) 4.92mhz (from pll) 1.57mhz (from pll) -- -- mpu_div clk. divider yes yes yes yes -- -- ice yes yes yes yes -- -- dio pins yes yes yes yes -- -- watchdog timer yes yes yes yes -- -- lcd yes yes yes yes yes -- lcd boost yes yes yes yes yes eeprom interface (2 - wire) yes yes yes yes -- -- eeprom interface (3 - wire) yes yes yes yes -- -- uart (full speed) yes yes yes yes -- -- optical tx modulation 38.4khz 38.9khz 38.4khz 38.9khz -- -- flash read yes yes yes yes -- -- flash page erase yes yes yes yes -- -- flash write yes yes yes yes -- -- ram read and write yes yes yes yes -- -- wakeup timer yes yes yes yes yes yes osc and rtc yes yes yes yes yes yes dram data preservation yes yes yes yes -- -- nv ram data preservation yes yes yes yes yes yes notes: 1. -- indicates that the corresponding circuit is not active 2. boost implies that the lcd boost circuit is active (i.e., lcd_vmode[1:0] = 10 ( i/o ram 0x2401[7:6] )) . t he lcd boost circuit requires a clock from the pll to function. thus, the pll is automatically kept active if lcd boost is active while in lcd mode, otherwise the pll is de - activated . downloaded from: http:///
71m6543f/71m6543g data sheet v2 77 3.2.1 brn mode in brn mode, most non - metering digital functions are active (as shown in table 61 ) i ncluding ice, uart, eeprom, lcd and rtc. in brn mode, the pll continues to function at the same frequency as m sn mode. it is up to the mpu to scale down the pll (using pll_fast, i/o ram 0x2200[4] ) or the mpu fre quency (using mpu_div[2:0], i/o ram 0x2200[2:0] ) in order to save power. from brn mod e, the mpu can choose to enter lcd or slp modes. when system power is re stored while the 71m6543 is in brn mode, the part automatical ly transition s to msn mode . the recommended minimum power configuration for brn mode is as follows: ? rce0 = 0x00 ( i/o ram 0x2709[7:0] ) - remote sensors disabled ? lcd_bat = 1 ( i/o ram 0x2402[7] ) - lcd powered from vbat ? lcd_vmode[1:0] = 0 ( i/o ram 0x2401[7:6] ) - 5v lcd boost disabled ? ce6 = 0x00 ( i/o ram 0x2106 ) - ce, rtm and chop are disabled ? mux_div[3:0] = 0( i/o ram 0x2100[7:4]) - the adc multiplexer is disabled ? adc_e = 0 ( i/o ram 0x2704[4] ) - adc disabled ? vref_cal = 0 ( i/o ram 0x2704[7] ) C v ref not driven out ? vref_dis = 1 ( i/o ram 0x2704[6] ) - vref disabled ? pre_e = 0 ( i/o ram 0x2704[5] - pre - amp disabled ? bcurr = 0 ( i/o ram 0x2704[3] ) - battery 100a current load off ? tmux[5:0] = 0x0e ( i/o ram 0x2502[5:0] ) C tmuxout output set to a dc value ? tmux2[4:0] = 0x0e ( i/o ram 0x250 3 [4:0] ) C tmuxout2 output set to a dc value ? ckgn = 0x24 ( i/o ram 0x2200 ) - pll set slow, and mpu_d iv[2:0] (i/o ram 0x2200[2:0] ) set to maximum ? temp_per [2:0] = 6 ( i/o ram 0x28a0[2:0] ) - temp measurement set to automatic every 512 s ? temp_bsel = 1 ( i/o ram 0x28a0[7] ) - temperature sensor monitors vbat ? pcon | = 1 ( sfr 0 x 87 ) - at the end of the main brn loop, halt the mpu and wait for an interrupt ? the baud rate registers are adjusted as needed ? all unused interrupts are disabled 3.2.2 lcd mode lcd mode may be commanded by the mpu at any time by setting the lcd_only control bit ( i/o ram 0x2 8b2 [6] ). however, it i s recommended that the lcd_only control bit be set by the mpu only after the 71m6543 has entered brn mode. for example, if the 71m6543 is in msn mode when lcd_only is set , the duration of lcd mode is very brief and the 71m6543 immediately 'wake s'. in lcd mode, v3p3d is disabled, and the vbat pin supplies the lcd current. before asserting lcd_only mode, it is recommended that the mpu minimize pll current by reducing the outp ut fre quency of the pll to 6.29 mhz (i.e., write pll_fast = 0, i/o ram 0x2200[4] ). the lcd boost system requires a clock from the pll for its operation . thus, if the lcd boost system is enabled (i.e., lcd_vmode[1:0] = 10, i/o ram 0x2401[7:6] ), then the pll is automatically kept active during lcd mode, otherwise the pll is de - activated. in lcd mode, the data contained in the lcd_seg registers is displayed using the segment driver pins. up to two lcd segments connected to the pins segdio22 and segdio23 can be made to blink without the involvement of the mpu, which is disabled in lcd mode. to minimize battery power consumption, only segments that are used should be enabled. after the transition from lcd mode to msn or brn mode, the pc (program counter) is at 0x0000, the xram is in an undefined state, and c onfiguration i/o ram bits are reset (see table 70 for i/o ram state upon wake) . the d ata stored in non - volatile i/o ram locations is pre served in lcd mode (the shaded locations in table 70 are non - volatile). downloaded from: http:///
71m6543f/71m6543g data sheet 78 v2 3.2.3 slp mode the slp mode may be commanded by the mpu whenever main system power is absent by asserting the sleep bit (i/o ram 0x28b2[7]) . the purpose of the slp mode is to consume the least power while still maintaining the rtc, temperature compensation of the rtc, and the non - volatile portions of the i/o ram. in slp mode, the v3p3d pin is disconnected, removing all sources of leakage from vbat and v3p3sys. the non - volatile memory domain and the basic functions, such as temperature sensor, oscillator, and rtc, are powered by the vbat_rtc input. in this mode, the i/o configuration bi ts, lcd configuration bits, and nv ram values are preserved and rtc and oscillator continue to run. this mode can be exited only by system power - up or one of the wake methods described in 3.4 wake - up behavi or . if the sleep bit is asserted when v3p3sys pin power is present (i.e., while in msn mode), the 71m6543 enters slp mode, resetting the internal wake signal, at which point the 71m6543 begins the standard wake from sleep procedures as described in 3.4 wake - up behavior . after the transition from slp mode to msn or brn mode the pc is at 0x0000, the xram is in an undefined state, and the i/o ram is only partially preserved (see the descr iption of i/o ram states in 5.2 ). the non - volatile sections of the i/o ram are preserved unless reset goes high. downloaded from: http:///
71m6543f/71m6543g data sheet v2 79 3.3 fault and reset behavior 3.3.1 events at power - down power fa ult detection is performed by internal comparators that monitor the voltage at the v3p3a pin and also monitor the internally generated vdd pin voltage (2.5 vdc). the v3p3sys a nd v3p3a pins must be tied together at the pcb level, so that the comparators, wh ich are internally connected only to the v3p3a pin, are able to simultaneously monitor the common v3p3sys and v3p3a pin v oltage. the following discussion assumes that the v3p3a and v3p3sys pins are tied together at the pcb level. during a power failure, as v3p3a falls, two thresholds are detected: ? the first threshold, at 3 .0 vdc ( vstat[2:0] = 001 , sfr 0xf9[2:0] ) , warns the mpu that the analog modules are no longer accurate. other than warning the mpu, the hardware takes no ac tion when this threshold is crossed. this comparison produces an internal bit named v3oka . ? the second threshold, at 2.8 vdc, cause s the 71m6543 to switch to battery power. this switching happen s while the flash and ram systems are still able to read and write. this comparison pr oduces an internal bit named v3ok . the power quality is reflected by the vstat[2:0] register in i/o ram space, as shown in table 62 . the vstat[2:0] register is located at sfr address f9 and occupies bits 2 : 0. the vstat[2:0] field can only be read. in addition to the state of the main power, the vstat[2:0] register provide s information about the internal vdd voltage under battery power. note that if system power (v3p3a) is above 2.8 vdc , the 71m6543 always switch es from battery to system power. table 62 : vstat[2:0] (sfr 0xf9[2:0]) vstat[2:0] description 000 system power ok. v3p3a > 3.0 vdc . analog modules are functional and accurate. 001 system power is l ow. 2.8 vdc < v3p3a < 3.0 vdc . analog modules not accurate. switch over to battery power is imminent. 010 the ic is on b att ery power and vdd is ok. vdd > 2.25 vdc . the ic has f ull digital functionality. 011 the ic is on b attery power and 2.25 vdc > vdd > 2.0 vdc . flash write operation s are inhibited. 101 the ic is on b attery power and vdd < 2.0, which means that the mpu is nearly out of vol tage. a reset occur s in 4 cycles of th e crystal clock ck32 . the response to a system power fault is almost entirely controlled by fi rmware. during a power failure, system power slowly fall s . thi s fall in power is monitored by internal comparator s that cause the hardware to automatically switch over to taking power from the v bat input. an interrupt notifies the mpu that the part is now battery powered. at this point, it is the mpu s responsibility to reduce power by slowing the clock rate, disabling the pll, etc. precision analog components such as the bandgap reference, the bandgap buffer, and the adc are powered only by the v3p3a pin and become inaccurate and ultimately unavailable as the v3p3a pin voltage continues to drop (i.e., circuits powered by the v3p3a pi n are not backed by the vbat pin) . when the v3p3a pin falls below 2.8 vdc, the adc clocks are halted and the am plifiers are unbiased . meanwhile, control bits such as adc_e bit (i/o ram 0x2704[4]) are not affected, since their i/o ram storage is powered from the vdd pin (2.5 vdc). the vdd pin is supplied wi th power through an internal 2.5 vdc regulator that is connected to the v3p3d pin. in turn, the v3p3d pi n is switched to receive power from the vbat pin when the v3p3sys pin drops below 3.0 vdc. note t hat the v3p3sys and v3p3a pins are typically tied together at the pcb level. downloaded from: http:///
71m6543f/71m6543g data sheet 80 v2 3.3.2 ic behavior at low battery voltage when system power is not present, the 71m6543 relies on the vbat pin for po wer. if the vbat voltage is not sufficient to maintain vdd at 2.0 vdc or greater, the mpu can not operate reliably. low vbat voltage can occur while the part is operating in brn mo de, or while it is dormant in slp or lcd mode. two cases can be distinguished, depending on mpu code: ? case 1: system power is not present , and the part is waking from slp or lcd mode. in this case, the hardware checks the value of vdd to determine if processor operation is possible. if it is not possible, the part configures itself for brn operation, and holds the proces sor in reset (wake=0). in this mode, vbat powers the 1.0 vdc reference for the lcd system, the vdd regulator, the pll, and the fault comparator. the part remain s in this waiting mode until vdd becomes high due to system power being applied or the vbat battery being replaced or recharged. ? case 2: the part is operating under vbat power and vstat [2:0] (sfr 0xf9[2:0]) becomes 101, in dica ting that vdd falls below 2.0 vdc . in this cas e , the firmware has two choices: 1) one choice is to assert the sleep bit ( i/o ram 0x28b2[7]) immediately. this assertion preserve s the remaining charge in vbat. of course, if the battery voltage is not incr eased, the 71m6543 enter s case 1 as soon as it tries to wake up. 2) the alternative choice is to enter the waiting mode described in case 1 immediately. specifically, if the firmware does not assert the sleep bit , the hardware reset s the processor four ce32 clock cycles (i.e. 122 s) after vstat [2:0] becomes 101 and, as described in case 1, it begin s waiting for vdd to become greater than 2 .0 vdc . the mpu wake s up when system power returns , or when vdd becomes greater than 2.0 vdc . in either case, when vdd recovers, and when the mpu wakes up, the wf_badvdd flag ( i/o ram 0x28b0[2] ) can be read to determine that the processor is recovering from a bad vbat condit ion. the wf_badvdd fl ag remain s set until the next time wake falls. this flag is independent of the oth er wf flags. in all cases, low vbat voltage does not corrupt rtc operation, the state of nv memory, or the state of non - volatile memory. these circuits depend on the vbat_rtc pin for power. 3.3.3 reset sequence when the reset pin is pulled high, all digital activity in the chip stops, with the exception of the oscillator and rtc. additionally, all i / o ram bits are forced to their rst state. a r eliable reset does not occur unti l reset has been high at least for 2 s. note that tmux and the rtc are not reset unless the test pin is pulled high while reset is high . the reset control bit ( i/o ram 0x 2200[3] ) performs an identical reset to the reset pin except that a significan tl y shorter reset timer is used. once initiated, the reset sequence wait s until the reset timer times out. the time out occur s in 4100 ce32 cycles (125 ms) , at which time the mpu begin s executing its pre - boot and boot sequences from address 0x0000. see 2.5.1.1 for a detailed description of the pre - boot and boot sequences . if system power is not present, the reset timer duration is two ce32 c ycles, at which time the mpu begin s executing in brn mode, starting at address 0x0000. a softer form of reset is initiated when the e_rst pin of the ice interface is pulled low . this event causes the mpu and other registers in the mpu core to be reset but does not reset the remainder of the 71m6543 . it does not trigger the reset sequence. this type of reset is intended to reset the mpu program, but not to make other changes to the chips state. 3.3.4 watchdog timer (wdt) reset the watchdog timer (wd t ) i s described in 2.5.13 . a status bit, wf_ovf (i/o ram 0x28b0[4]) , is set when a wdt overflow occurs. similar to the other wake flags, this bit is powered by the non - volatile supply and can be read by the mpu to determine if the part is initializing after a wd overflow event or after a power - up . the wf_ovf bit is clea red by the reset pin. there is no internal digital state that could deactivate the wd t . for debug purposes, however, the wd t can be disabled by raising the ice_e pin to 3.3 vdc . downloaded from: http:///
71m6543f/71m6543g data sheet v2 81 in normal operation, the wd t is reset by periodically writing a one to the wd_rst control bit i/o ram 0x28b4[7]) . the watchdog timer is also reset when the 71m6543 wakes from lcd or slp mode, and when ice_e=1. 3.4 wake - up behavior as described above, the part always wake s up in msn mode when system power is restored . as stated in 3.2 battery modes , t ransition s from both lcd and slp mode to brn mode can be initiated by a wake - up timer time out, when the p ushbutton (pb) input is activated, a rising edge on segdio4 , or a high logic level on segdio52 or segdio55, or by activity on the rx or opt_rx pi ns. 3.4.1 wake on har dware events the following pin signal events wake the 71m6543 from slp or lcd mode: a high level on t he pb pin, either edge on the rx pin, a rising edge on the segdio4 pin, a high level on the segdio52 pin, or a high level on the segdio55 pin or either edge on the opt_rx pin. see table 63 for de - bounce details on each pin and for further details on the opt_rx/segdio55 pin. t he segdio4 , seg dio52, and seg dio55 pins must be configured as dio inputs and their wake enable ( ew_x bits) must be set. in slp and lcd modes, the mpu is held in reset and cannot poll pins or react to interrupts. when one of the hardware wake events occurs, the internal wake signal rises and within three ck32 cycles the mpu begins to execute. the mpu can de ter mine which one of the pins awakened it by checking the wf_pb , wf_rx , wf_segdio4 , wf_dio52 , or wf_dio55 flags (see table 63 ) . if the part is in slp or lcd mode, it can be awakened by a high level on the pb pin. this pin is normally pulled to gnd and can be connected externally so it may be pulled high by a push button depression . some pins are de - bounced to reject emi noise. detection hardware ignore s all transitions after the initial transition . table 63 shows which pins ar e equipped with de - bounce circuitry. pins that do not have de - bounce circuits must still be high for at least 2 s to be recognized. the wake enable and flag bits are shown in table 63 . the wake flag bits are set by hardware when the mpu wakes from a wake event. note that the pb flag is set whenever the p b is pushed, even if the part is already awake. table 65 lists the events that clear the wf flags. in addition to push buttons and timers, the part can also reboot due to the rese t pin, the reset bit (i/o ram 0x2200[3]) , the wdt, the cold start detector, and e_rst. as seen in table 63 , each of these mechanisms has a flag bit to alert the mpu to the source of the wakeup. if the wakeup is caused by return of system power, there is no active wf flag and the vstat[2:0] field ( sfr 0xf9[2:0]) indicate s that system power is stable . table 63 : wake enable and flag bits wake enable wake flag de - bounce description name location name location wake_arm 28b2[5] wf_tmr 28b1[5] no wake on timer. ew_pb 28b3[3] wf_pb 28b1[3] yes wake on pb. * ew_rx 28b3[4] wf_rx 28b1[4] 2 s wake on either edge of rx. ew_dio4 28b3[2] wf_dio4 28b1[2] 2 s wake on segdio4. ew_dio52 28b3[1] wf_dio52 28b1[1] yes wake on segdio52. * ew_dio55 28b3[0] wf_dio55 28b1[0] yes opt_rxdis = 1: wake on dio55 with 64 ms de - bounce .* opt_rxdis = 0: wake on either edge of opt_rx with 2 s de - bounce . opt_rxdis: i/o ram 0x2457[2] always enabled wf_rst 28b0[6] 2 s wake after reset. always enabled wf_rstbit 28b0[5] no wake after reset bit. always enabled wf_erst 28b0[3] 2 s wake after e_rst. (ice must be enabled) downloaded from: http:///
71m6543f/71m6543g data sheet 82 v2 wake enable wake flag de - bounce description name location name location always enabled wf_ovf 28b0[4] no wake after wd reset. always enabled wf_cstart 28b0[7] no wake after cold start - the first application of power. always enabled wf_badvdd 28b0[2] no wake after insufficient vbat voltage. * this pin is sampled every 2 ms and must remain high for 64 ms to be decl ared a valid high level. this pin is high - level sensitive. table 64 : wake bits name location rst wk dir description ew_dior 28b3[2] 0 C r/w connects segdio4 to the wake logic and permits segdio4 rising to wake the part. this bit has no effect unless segdio4 is configured as a digital input. ew_dio 52 28b3[1] 0 C r/w connects dio52 to the wake logic and permits dio52 high level to wake the part. this bit has no effect unless dio52 is configured as a digital input. ew_dio 55 28b3[0] 0 C r/w connects dio55 to the wake logic and permits dio55 high level to wake the part. this bit has no effect unless dio55 is configured as a digital input. wake_arm 28b2[5] 0 C r/w arms the wake timer and loads it with the value in wake_tmr ( i/o ram 0x2880 ) register . when slp or lcd mode is asserted by the mpu, the wake timer become s active. ew_pb 28b3[3] 0 C r/w connects the pb pin to the wake logic and permits pb high level to wake the part. pb is always configured as an input. ew_rx 28b3[4] 0 C r/w connects the rx pin to the wake logic and permits rx rising to wake the part. see 3.4.1 for de - bounce issues. wf_dio 4 28b1[2] 0 C r segdio4 flag bit. if segdio4 is configured to wake the part, this bit is set whenever segdio4 rises . it is held in reset if segdio4 is not configured for wakeup. wf_dio 52 28b1[1] 0 C r seg dio52 flag bit. if seg dio52 is configured to wake the part, this bit is set whenever seg dio52 is a high level . it is held in reset if seg di o 52 is not configured for wakeup. wf_dio 55 28b1[0] 0 C r seg dio55 flag bit. if seg dio55 is configured to wake the part, this bit is set whenever seg dio55 is a high level . it is held in reset if segdio 55 is not configured for wakeup. wf_tmr 28b1[5] 0 C r indicates that the wake timer caused the part to wake up. wf_pb 28b1[3] 0 C r indicates that the pb pin caused the part to wake. wf_rx 28b1[4] 0 C r indicates that rx pin caused the part to wake. wf_rst wf_rstbit wf_erst wf_cstart wf_badvdd 28b0[6] 28b0[5] 28b0[3] 28b0[7] 28b0[2] * * * * * C r indicates that the rst pin, e _ rst pin, reset bit ( i/o ram 0x2200[3]) , the cold start detector, or low voltage on the vbat pin caused the part to re set. *see table 65 for details. downloaded from: http:///
71m6543f/71m6543g data sheet v2 83 table 65 : clear events for wake flags flag wake on: clear events wf_tmr timer expiration wake falls wf_pb pb pin high level wake falls wf_rx either edge rx pin wake falls wf_dio4 segdio4 rising edge wake falls wf_dio52 segdio52 high lev el wake falls wf_dio55 if opt_rxdis = 1 ( i/o ram 0x2457[2] ), wake on segdio55 high if opt_rxdis = 0 wake on either edge of opt_rx wake falls wf_rst reset pin driven high wake falls, wf_cstart, wf_rstbit, wf_ovf, wf_badvdd wf_rstbit reset bit is set ( i/o ram 0x2200[3] ) wake falls, wf_cstart, wf_ovf, wf_badvdd, wf_rst wf_erst e_rst pin driven high and the ice interface must be enabled by driving the ice_e pin high. wake falls, wf_cstart, wf_rst, wf_ovf, wf_rstbit wf_ovf watchdog (wd) reset wake falls, wf_cstart, wf_rstbit, wf_badvdd, wf_rst wf_cstart cold - start (i.e., after the application of first power) wake falls, wf_rstbit, wf_ovf, wf_badvdd, wf_rst note: wake falls implies that the internal wake signal has been reset, which happens automatically upon entry into lcd mode or sleep mode (i.e., when the mpu sets the lcd_only bit ( i/o ram 0x28b2[6] ) or the sleep ( i/o ram 0x28b2[7] ) bit) . when the internal wak e signal resets, all wake flags are reset. since the various wake flags are automatically reset when wake falls, it is not necessary for the mpu to reset these flags before entering lcd mode or sleep mode. also, other wake events can caus e the wake flag to reset, as indicated above (e.g., the wf_rst flag can also be reset by any of the following flags setting: wf_cstart , ws_rstbit , wf_ovf , wf_badvdd ) 3.4.2 wake on timer if the part is in slp or lcd mode, it can be awakened by the wake t imer. until th is timer times out, the mpu is in reset due to the internal wake signal being low. when the wake t imer times out, wake rises and within three ck32 cycles, the mpu begins to execute. the mpu can determine that the timer wok e it by checking the wf_tmr (i/o r am 0x28b1[2] ) wake flag. the wake t imer begins timing when the part enters lcd or slp mode. its duration is co ntrolled by the wake_tmr[7:0] register (i/o ram 0x2880) . the timer duration is wake_tmr[7:0] +1 seconds. the wake t imer is armed by setting wake_arm = 1 ( i/o ram 0x28b2[5] ) . it must be armed at least three rtc cycles before either slp or lcd modes are initiated. setting wake_arm presets the timer with the value in wake_tmr and rea dies the timer to start when the mpu writes to the sleep (i /o ram 0x28b2[7] ) or lcd_only (i/o ram 0x28b2[6]) bits. the timer is neither reset nor disarmed when the mpu wakes - up. thus, once armed and set, the mpu continue s to be awakened wake_tmr [7:0] seconds after it requests slp mode or lcd mode (i.e., once written, the wake_tmr[7:0] register holds its value and does not have to be re - written each time the mpu enters slp or lcd mode. also, since wake_tmr[7:0] is non - volatile, it also holds its value through resets and power failures). 3.5 data flow and mpu/ce communic ation the data flow between the compute engine ( ce ) and the mpu is shown in figure 26 . in a typical application , t he 32 - bit ce se quen tially processes the samples from the adc inputs , performing calculations to measure downloaded from: http:///
71m6543f/71m6543g data sheet 84 v2 active power (wh), reactive power (varh), a 2 h, and v 2 h for four - quadrant metering . these measurements are then accessed by the mpu, processed further and output using the peripheral devic es available to the mpu. both the ce and multiplexer are controlled by the mpu via shared regist ers in the i/o ram and in ram. the ce outputs a total of six discrete signals to the mpu. these consist of four pulses and two interrupts: ? ce_busy ? xfer_busy ? wpulse, vpulse (pulses for active and reactive energy) ? xpulse, ypulse (auxiliary pulses) these interrupts are connected to the mpu interrupt service inputs as external inter rupts. ce_busy indicates that the ce is actively processing data. this signal occurs once every multiplexer cycle (typically 396 s), and indicates that the ce has updated status information in it s cestatus register (ce ram 0x80) . xfer_busy indicates that the ce is updating data to the output region of t he ram. this update occur s when ever the ce has finished generating a sum by completing an accumulation interv al determ ined by sum_samps[12:0], i/o ram 0x2107[4:0], 2108[7:0], (typically every 1000 ms). interrupts to the mpu occur on the falling edges of the xfer_busy and ce_busy signals. wpulse and vpulse are typically used to signal energy accumulation of real (wh) and reactive (varh) energy. tying wpulse and vpulse into the mpu interrupt system can supp ort pulse counting. xpulse and ypulse can be used to signal events such as sags and zero crossings of the mains voltage to the mpu. tying these outputs into the mpu interrupt system reliev es the mpu from having to read the cestatus register at every occurrence of the ce_busy interrupt in order to detect s ag or zero crossing events. refer to 5.3 ce interface description on page 116 for additional information on setting up the device using the mpu firmware. figure 26 : mpu/ce data flow mpu ce i/o ram (configuration ram) pulses samples wpulse vpulse xpulseypulse control processed metering data mux control control interrupts ceconfig cestatus xram ce_busy xfer_busy downloaded from: http:///
71m6543f/71m6543g data sheet v2 85 4 application information 4.1 connecting 5 v devices all digital input pins of the 71m6543 are compatible with external 5 v devi ces. i/o pins configured as inputs do not require current - limiting resistors when they are connected to external 5 v devices. 4.2 directly connected sensor s figure 27 through figure 30 show voltage - sensing resistive dividers, current - sensing current transformers (cts) and current - sensing res is tive shunts and how they are connected to the voltage and current inputs of the 71m6543 . all input signals to the 71m6543 sensor inputs are voltage signals providing a scaled representation of either a sensed voltage or current. the analog input pins of the 71m654 3 are designed for sensors with low source impedance. rc filters with resista nce values higher than those implemented in the demo boards must not be used . r efer to the demo board schematics for complete sensor input circuits and corresponding component values. v in r out v3p3a vadcn (n = 8, 9 or 10) figure 27 : resistive voltage divide r (voltage sensing) i in iadcn v3p3a v out i out r burden ct 1:n noise filter (n = 0,1,...7) figure 28 . ct with single - ended input connection (current sensing) i in iadcn iadcn+1 v3p3a v out i out r burden ct 1:n bias network and noise filter (n = 0, 2, 4 or 6) figure 29 : ct with differential in put connection (current sensing) i in r shunt iadcn iadcn+1 v3p3a v out bias network and noise filter (n = 2, 4 or 6) figure 30 : differential resistive shunt connections (current sensing) downloaded from: http:///
71m6543f/71m6543g data sheet 86 v2 4.3 system s using 71m6xx 3 isolated sensor s and current shunts figure 31 shows a typical connection for current shunt sensors; using the 71m 6xx3 ( polyphase ) isolated s ensor s . note that one shunt current sensor is connected without isolation, which is th e neutral current sensor in this example ( connected to pins ia dc0 - ia dc1 ) . each 71m 6xx3 device is electrically isolated by a low - cost pulse transformer. th e 71m6543 current sensor inputs must be configured for remote sensor communication s , as described in 2.2.8 71m6xx3 isolated sensor interface (page 22 ). flexible remapping using the i/o ram registers muxn_sel[3:0] allows the sequence of analog input pins to be different from the standar d configuration (a corresponding ce code must be used) . see figure 2 for the afe configuration corresponding to figure 31 . mpu rtc timers iadc0 vadc 8 ( va ) iadc 2 vadc9 (vb) xin xout rx tx txrx com0...5 v3p3a v3p3 sys vbat vbat_rtc iadc 4 vadc10 (vc) seg gnda gndd seg/dio dio ice c ba neutral load 8888.8888 pulses, dio ir amr power fault comparator modul- ator serial ports oscillator/ pll mux and adc lcd driver dio, pulses compute engine flash memory ram 32 khz regulator shunt current sensors power supply 71m6543f/ 71m6543g temperature sensor vref iadc 6 battery pwr mode control wake-up neutral i 2 c or wire eeprom 9/17/2010 iadc1 iadc 3 iadc 5 iadc 7 rtc battery v3p3d battery monitor spi interface host lcd display resistor dividers pulse transformers 3x 71m6xx3 note: this system is referenced to neutral 71m6xx371m6xx3 71m6xx3 } in* } ia } ib } ic *in = neutral current fig ure 31 : system using three - remotes and one - local (neutral) sensor downloaded from: http:///
71m6543f/71m6543g data sheet v2 87 4.4 system using current transformers figure 32 shows a polyp hase system using four current transformers to support optional neutral current sensing for anti - tamper purposes. the neutral current sensing ct can be omitted if neutral current sens ing is not required. the system is referenced to neutral (i.e., the neut ral rail is tied to v3p3a and v3p3sys). mpu rtc timers iadc2 vadc 8 ( va ) iadc 4 vadc9 (vb) xin xout rx tx txrx com0...5 v3p3a v3p3 sys vbat vbat_rtc iadc 6 vadc10 (vc) seg gnda gndd seg/dio dio ice a bc neutral load 8888.8888 pulses, dio ir amr power fault comparator modul- ator serial ports oscillator/ pll mux and adc lcd driver dio, pulses compute engine flash memory ram 32 khz regulator current transformers power supply 71m6543f/ 71m6543g temperature sensor vref iadc 0 battery pwr mode control wake-up neutral i 2 c or wire eeprom 9/17/2010 iadc3 iadc 5 iadc 7 iadc 1 rtc battery v3p3d battery monitor spi interface host lcd display resistor dividers note: this system is referenced to neutral } ia } ib } ic } in* *in = optional neutral current figure 32 . system using current transformers downloaded from: http:///
71m6543f/71m6543g data sheet 88 v2 4.5 metrology temperature compensation 4.5.1 temperature compensation since the vref band - gap amplifier is chopper - stabilized, as set by the chop_e[1:0] (i/o ram 0x2106[3:2]) control field , the dc offset voltage, which is the most significant long - term drift mechanism in the voltage reference s (vref), is automatically removed by the chopper circuit. both the 71m6543 and the 71m6xx3 feature chopper circuits for their respective vref voltage reference. since the variation in the bandgap reference voltage (vref) is the major cont ributor to me asurement error across temperatures , maxim implements a two - step procedure to trim and characterize the vref voltage reference during the device manufacturing process . the first step in the process is applied to all parts ( 71m6543f , 71m6543g) . in this first step, the reference voltage (vref) is trimmed to a target value of 1.195v. during this trimming process, the trimt[7:0] ( i/o ram 0x2309 ) value is stored in non - vol atile fuses. trimt[7:0] is trimmed to a value that results in minimum vref variation with temperature. for the 71m6543f and 71m6543g device s , the trimt[7:0] value can be read by the mpu during initialization in order to calculate parabolic temperature compensation coefficients suitable for eac h individual 71m6543f and 71m6543g device. the resulting temperature coefficient for vref in the 71m6543f an d 71m6543g is 40 ppm/ c. considering the factory calibration temperature of vref to be +22c and the industri al temperature range ( - 40 c to +85c), the vref error at the temperature extremes for the 71m6543f and 71m6543g device s can be calculated as: % 252 .0 2520 / 40 ) 22 85( += += ? ? ppm c ppm c c o o o and % 248 .0 2480 / 40 ) 22 40 ( ?= ?= ? ? ? ppm c ppm c c o o o the above calculation implies that both the voltage and the current measurements are indi vidually subject to a theoretical maximum error of approximately 0.25%. when the volt age sample and current sample are multiplied together to obtain the energy per sample, the voltage error and current error combine resulting in approximately 0.5% maximum energy measurement error. how ever, this theoretical 0.5% error considers only the voltage reference (vref) as an error sour ce. in practice, other error sources exist in the system. t he principal remaining error sources are the current sensors (shunts or cts) and their corresponding signal conditioning circuits, and the resistor voltage divider used to measure the voltage. the 71m6543f and 71m6543g device s should be used in class 1% designs, to allow margin for the other error sources in the system. the preceding discussion in this section also applies to the 71m6603 (0.5%), 71m611 3 (0.5%) and 71m6203 (0.1%) remote sensors. refer to the 71m6xxx data sheet for details. 4.5.2 temperature coefficients for the 71m6543f and 71m6543g the equations provided below for calculating tc1 and tc2 apply to the 71m6543f and 71m6543g . in order to obtain tc1 and tc2, the mpu reads trimt[7:0] ( i/o ram 0x2309 ) and uses the tc1 and tc2 equations provided . ppmc and ppmc2 are then calculated from tc1 and tc2, as shown. the resulting tracking of the refer ence voltage (vref) is within 4 0 ppm/c . trimt c v tc ? ? = 95.4 275 ) / (1 trimt c v tc ? ? ?= 00028 .0 557 .0 ) / (2 2 1 4632 .22 tc ppmc ? = 2 116 . 1150 2 tc ppmc ? = see 4.5.4 and 4.5.5 below for further temperature compensation details. downloaded from: http:///
71m6543f/71m6543g data sheet v2 89 4.5.3 temperature coefficients for the 71m6 xx 3 refer to the 71m6xxx data sheet for the eq u ations that are applicable to each 71m6xx3 part number and the corresponding temperature coefficients. 4.5.4 temperature compensation for vref and shunt sensors this section discusses metrology temperature compensation for the meter designs where current shunt sensors are used in conjunction with the 71m6xx3 remote isolated sensors, as shown in figure 31 . s ensors that are directly connected to the 71m6543 are affected by the voltage v ariation in the 71m6543 vref due to temperature. on the other hand, shunt sensors that are connected to 71m 6xx3 remote sensor are affected by the vref in the 71m 6xx3 . the vref in both the 71m6543 and 71m 6xx3 can be compensated digitally using a second - order polynomial function of temperature. the 71m6543 and 71m 6xx3 feature temperature sensors for the purposes of temperature compensating their correspond ing vref. the compensation computations must be implemented in mpu firmware . referring to figure 31 , the vadc8 ( va ) , vadc9 ( vb ) and vadc10 ( vc ) voltage sensors are always directly connected to the 71m6543. thus, the precision of the voltage sensors is primarily affected by vref in the 71m6 54 3 . the temperature coefficient of the resistors used to implement the voltage divider s for the voltage sensors (see figure 27 ) determine the behavior of the voltage division ratio with respect to temperature. it is recommended to use resistors with low temperature coe fficients, while forming the entire voltage divider using resistors belonging to the same technology family, in order t o minimize the temperature dependency of the voltage division ratio . the resistors must also have suitable voltage ratings. the 71m654 3 also may have one local current shunt sensor that is connected directly to it via the iadc0 - iadc1 input pins, and therefore this local current sensor is also affected by the v ref in the 71m654 3 . the shunt current sensor resistance has a temperature dependency, which also may require compensation , depend ing on the required accuracy class . the i adc2 - iadc3 , i adc4 - iadc5 and i adc6 - iadc7 current sensors are isolated by the 71m 6xx3 and depend on the vref of the 71m 6xx3 , plus the variation of the corresponding remote shunt current sensor with temperature. the mpu has the responsibility of computing the necessary sample gain com pensation values required for each sensor channel based on the sensed temperature. maxim provides demonstration code that implements the gain_adj x compensation equation shown below. the resulting gain_adj x values are stored by the mpu in five ce ram locations gain_adj0 - gain_adj 5 ( ce ram 0x40 - 0x4 4 ). the demonstration code thus provides a suitable implementation of temperature compensation, but other methods are possible in mpu firmware by utilizing the on - chip temperature sensors while storing the sample gain adjustment results in the ce ram gain_adj x storage locations for use by the ce . the demonstration code maintains five separate sets of ppmc and ppmc 2 coefficients and comp utes five separate gain_adj x values based on the sensed temperature using the equation below: 23 2 14 2 2 _ 100 2 _ 10 16385 _ ppmc x temp ppmc x temp adjx gain ? ? + ? ? + = the gain_adj x values stored by the mpu in ce ram are used by the ce to gain adjust (i.e., multiply) the sample in each corresponding sensor channel. a gain_adj x value of 16,384 (i.e . , 2 14 )corresponds to unity gain, while values less than 16,384 attenuate the samples and values greater t han 16,384 amplify the samples . in the above equation , temp_x is the deviation from nominal or calibration temperature expressed in mul tiples of 0.1 c . t he 10x and 100x factors seen in the above equation are due to 0.1 o c scaling of temp_x . for example, if the calibration (reference) temperature is 22 o c and the measured temperature is 27 o c, then 10* temp_x = (27 - 22) x 10 = 50 (decimal), which represents a +5 o c deviation from 22 o c. in the demonstration code, temp_x is calculated in the mpu from the stemp[10:0] temperature sensor reading using the equation provided below and is scaled in 0.1c units. see 2.5.5 71m6 543 temperature sensor on page 53 for the equation to calculate temperature in degrees c from the stemp[10:0] value. table 66 shows the five gain_adj x equation output storage location s and the voltage or current sensor channels for which they compensate for the 1 local / 3 remote configuration shown in figure 31 . downloaded from: http:///
71m6543f/71m6543g data sheet 90 v2 table 66 : gain_adjn compensation channels ( figure 2 , figure 31 , table 1 ) gain adjustment output ce ram address sensor channel (s) (pin names) compensation for: gain_adj0 0x40 vadc8 ( va ) vadc9 ( vb ) vadc10 ( vc ) vref in 71m6543 and voltage divider resistors gain_adj 1 0x41 iadc0 - iadc1 vref in 71m6543 and shunt (neutral current) gain_adj 2 0x42 iadc2 - iadc3 vref in 71m6xx3 and shunt (phase a) gain_adj 3 0x43 iadc4 - iadc5 vref in 71m6xx3 and shunt (phase b) gain_adj 4 0x44 iadc6 - iadc7 vref in 71m6xx3 and shunt (phase c) in the demonstration code, the shape of the temperature compensation second - order parabolic curve is determined by the values stored in the ppmc (1 st order coefficient) a nd ppmc2 (2 nd order coefficient) , which are typically setup by the mpu at initialization time from values that are stored i n eeprom. to disable temperature compensation in the demonstration code, ppmc and ppmc2 are both set to zero for each of the five gain_adj x channels. to enable temperature compensation, the ppmc and ppmc2 c oefficients are set with values that match the expected temperature variation of the shunt current sensor (if required ) and the corresponding vref voltage reference (summed together) . the shunt sensor requires a second order polynomial compensation which is determined by the ppmc and ppmc2 coefficient s for the corresponding current measurement channel. the corresponding vref voltage reference also requires the ppmc and ppmc2 coefficients to match the second order temperature behavior of the voltage reference. the ppmc and ppmc2 values associated with the shunt and with the corresponding vref are summed together to obtain the compensation coefficients for a given current - sensing channel (i.e., the 1 st order ppmc c oefficients are summed together, and the 2 nd order ppmc2 coefficients are summed together). in the 71m6543f and 71m6543g , the required vref compensation coefficients ppmc and ppmc2 are calculated from readable on - chip non - volatile fuses (see 4.5.2 temperature coefficients for the 71m6543f ). these coefficients are designed to achieve 40 ppm/c for vref in the 71m6543f and 71m6543g . ppmc and ppmc2 coefficients are similarly calculated for the 71m6xx3 remote sensor (see 4.5.3 temperature coefficients for the 71m6xx3 ). for the current channels, to determine the ppmc and ppmc2 coefficient s for the shunt current sensors , the designer must either know the average temperature curve of the shunt from its manufacturers data sheet or obtain the se coefficients by laboratory characterization of the shunt used in the design. 4.5.5 temperature compensation of vref and current transformers this section discusses metrology temperature compensation for meter designs wh ere current transformer (ct) sensors are used, as shown in figure 32 . sensors that are directly connected to the 71m6543 are affected by the voltage variation in the 71m6543 vref due to temperature. the vref in the 71m6543 can be compensated digitally us ing a second - order polynomial function of temperature. the 71m6543 features a temperature sensor f or the purposes of temperature compensating its vref. the compensation computations must be implemented in mpu firmware and written to the corresponding gain_adjx ce ram location . referring to figure 32 , the vadc8 ( va ) , vadc9 ( vb ) and vadc10 ( vc ) voltage sensors are directly connected to the 71m6543. thus, the precision of the voltage sensors is primarily affected by vref in the 71m654 3 . the temperature coefficient of the resistors used to implement the vol tage dividers for the voltag e sensors (see figure 27 ) determine the behavior of the voltage division ratio with respect to temperature. it is recommended to use resistors with low temperature coefficients, while form ing the entire voltage divider using resistors belonging to the same technology family, in order to minimize the temperature dependency of the voltage division ratio. the resistors must also have suitable voltage rat in gs. the current transformers are directly connected to the 71m6543 and are therefore primarily affected by the vref temperature dependency in the 71m6543. for best performance, it is recommended to use the downloaded from: http:///
71m6543f/71m6543g data sheet v2 91 differential signal conditioning circuit, as shown in figure 29 , to connect the cts to the 71m6543. c urrent transformers may also require temperature compensation. the copper wire winding in the ct has dc resistance with a temperature coefficient, which makes the voltage delivered t o the burden resistor temperature dependent, and the burden resistor also has a temperature coefficient. thus, each ct sensor channel needs to compensate for the 71m6543 vref, and optionally for the temperature dependency of the ct and its burden resistor depending on the required accuracy class. the mpu has the responsibility of computing the necessary sample gain com pensation values required for each sensor channel based on the sensed temperature. maxim provides demonstration code that implements the gain_adj x compensation equation shown below. the resulting gain_adj x values are stored by the mpu in five ce ram locations gain_adj0 - gain_adj5 ( ce ram 0x40 - 0x 44 ). the demonstration code thus provides a suitable implementation of temperature compensation, but other methods are possible in mpu firmware by utilizing the on - chip temperature sensor while storing the sample gain adjustment results in the ce ram gain _adjn storage locations. the demonstration code maintains five separate sets of ppmc and ppmc 2 coefficients and computes five separate gain_adjn values based on the sensed temperature using the equation below: 23 2 14 2 2 _ 100 2 _ 10 16385 _ ppmc x temp ppmc x temp adjx gain ? ? + ? ? + = the gain_adjn values stored by the mpu in ce ram are used by the ce to gain adjust (i.e., multiply) the sample in each corresponding sensor channel. a gain_adj x value of 16,384 ( i.e. , 2 14 )corresponds to unity gain, while values less than 16,384 attenuate the samples and values greater t han 16,384 amplify the samples. in the above equation, temp_x is the deviation from nominal or calibration temperature expressed in mul tiples of 0.1 c . t he 10x and 100x factors seen in the above equation are due to 0.1 o c scaling of tem p_x . for example, if the calibration (reference) temperature is 22 c and the measured temperature is 27 c, then 10* temp_x = (27 - 22) x 10 = 50 (decimal), which represents a +5 c deviation from 22 c. in the demonstration code, temp_x is calculated in the mpu from the stemp[10:0] temperature sensor reading using the equation provided below and is scaled in 0.1c units. see 2.5.5 71m6543 temperature sensor on page 53 for the equation to calculate temperature in c from the stemp[10:0] reading. table 67 shows the five gain_adj x equation output storage locations and the voltage or current measurements for which they compensate. table 67 : gain_adj x compensation channels ( figure 3 , figure 32 , table 2 ) gain adjustment output ce ram address sensor channel(s) (pin names) compensa tion for: gain_adj0 0x40 vadc8 (va) vadc9 (vb ) vadc10 ( vc ) vref in 71m6543 and voltage divider resistors gain_adj 1 0x41 iadc0 - iadc1 vref in 71m6543, ct and burden resistor (neutral current ) gain_adj 2 0x42 iadc2 - iadc3 vref in 71m6 543, ct and burden resistor ( phase a ) gain_adj 3 0x43 iadc4 - iadc5 vref in 71m6 543, ct and burden resistor ( phase b ) gain_adj 4 0x44 iadc6 - iadc7 vref in 71m6 543, ct and burden resistor (phase c ) in the demonstration code, the shape of the temperature compensation second - order parabolic curve is determined by the values stored in the ppmc (1 st order coefficient) and ppmc2 (2 nd order coefficient), which are typically setup by the mpu at initialization time from val ues that are stored in eeprom. to disable temperature compensation in the demonstration code, ppmc and ppmc2 are both set to zero for each of the five gain_adj x channels. to enable temperature compensation, the ppmc and ppmc2 coefficients are set with values that match the expected vref temperature variation and optionally the downloaded from: http:///
71m6543f/71m6543g data sheet 92 v2 corresponding sensor circuit (i.e., the ct and burden resistor for current c hannels or the resistor divider network for the voltage channels) . in the 71 m6543f and 71m6543g , the required vref compensation coefficients ppmc and ppmc2 are calculated from readable on - chip non - volatile fuses (see 4.5.2 temperature coefficients for the 71m6543f ). these coefficients are designed to achieve 40 ppm / c for vref. 4.6 connecting i 2 c eeproms i 2 c eeproms or other i 2 c compatible devices should be connected to the dio pins segdio 2 and segdio3 , as shown in figure 33 . pullup resistors of roughly 10 k ? to v3p3d (to ensure operation in brn mode) should be used for both sdck and sdata signals . the dio_eex ( i/o ram 0x2456[7:6] ) field must be set to 01 in order to convert the dio pins segdio2 and segdio3 to i 2 c pins scl and sdata . figure 33 : i 2 c eeprom connection 4.7 connecting three - wire eeproms wire eeproms and other compatible devices should be connected to the dio pi ns segdio2 and segdio3 , as described i n 2.5.11 eeprom interface on page 65 . 4.8 uart0 (tx/rx) the uart0 rx pin should be pulled down by a 10 k ? resistor and additionally protected by a 100 pf ce ramic capacitor, as shown in figure 34 . figure 34 : connections for uart0 tx rx 71m6543 10 k 100 pf rx tx dio 2 dio 3 eeprom sdck sda ta v3p3d 10 k 10 k 71m6543 downloaded from: http:///
71m6543f/71m6543g data sheet v2 93 4.9 optical interface (uart1) the opt_tx and opt_rx pins can be used for a regular serial interface ( by connecting a rs_232 tran sceiver for example), or they can be used to directly operate optical components (for example, an infrared diode and phototransistor implementing a flag interface ) . figure 35 shows the basic connections for uart1 . the opt_tx pin becomes active when the control field opt_txe ( i/o ram 0x2456[3:2]) is set to 01 . the polarity of the opt_tx and opt_rx pins can be inverted with the configuration bits , opt_txinv (i/o ram 0x2456[0]) and opt_rxinv (i/o ram 0x2457[1]) , re spectively. the opt_tx output may be modulated at 38 khz when system power is present . modulation is not available in brn mode . the opt_txmod bit ( i/o ram 0x2456[1]) enables modulation . the duty cycle is controlled by opt_fdc[1:0] (i/o ram 0x2457[5:4] ) , which can select 50%, 25%, 12.5%, and 6.25% duty cycle . a 6.25% duty cycle means opt_tx is low for 6.25% of the period. the opt_rx pin uses digital signal thresholds. it may need an analog filter when receiving modulated opti cal signals. with modulation, an optical emitter can be operated at higher current than nominal , enabling it to increase th e distance along the optical path. if operation in brn mode is desired, the external components should be connected to v3p3d. however, it is recommended to limit the current to a few ma. figure 35 : connection for optical components 4.10 connecting the reset pin even though a functional meter does not necessarily need a reset switch, it is useful to have a reset push button for protot yping as shown in figure 36 , left side. the reset signal may be sourced from v3p3sys (functional in msn mode only), v3p3d ( msn and brn modes), or vbat (all modes, if a battery is present) , or from a combination of these sources, depending on the application. for a production meter, the reset pin should be protected by the by the externa l components shown in figure 36 , right side. r1 should be in the range of 100 ? and mounted as closely as possible to the ic. s ince the 71m6543 generates its own power - on reset, a reset button or circuitry, as sho wn in figure 36 , is only required for test units and prototypes. opt_tx r 2 r 1 opt_rx 71m6543 v3p3sys phototransistor led 10 k? 100 pf v3p3sys downloaded from: http:///
71m6543f/71m6543g data sheet 94 v2 figure 36 : external components for the reset pin: push - button (left), production circuit (right) 4.11 connecting the emulator port pins even when the emulator is not used, small shunt capacitors to ground (22 pf ) should be used for protection from emi as illustrated in figure 37 . production boards should have the ice_e pin connected to ground. figure 37 : external components for the emulator interface 4.12 flash programming 4.12.1 flash programming via the ice port operational or test code can be programmed into the flash memory using either an in - circuit emulator or the flash programmer module (tfp -2 ) available from maxim . the flash programming procedure uses the e_rst, e_rxtx, and e_tclk pins. 4.12.2 flash programming via the spi port it is possible to erase, read and program the flash memory of the 71m6543 via the spi p ort. see 2.5.12 for a detailed description. 4.13 mpu demonstration code all application - speci fic mpu functions mentio ned in 4 application information are featured in the demonstration c source code supplied by maxim . the code is available as part of the demo nstration kit for the 71m6543 . the demonstrati on kits come with the 71m6543 preprogrammed with demo nstration firmware and mounted on a functional sample meter demo board . the demo boards allow for quick and efficient evaluation of the ic without having to write firmware or having to supply an in - circuit emulator (ice). e_rst 71m6543 e_tclk 62 62 ? 62 ? 22 pf 22 pf 22 pf lcd segments ice_e v3p3d e_rxt (optional) r 1 reset 71m6543 gndd v3p3d r 2 vbat/ v3p3d reset switch 1k 0.1f 10k 71m6543 downloaded from: http:///
71m6543f/71m6543g data sheet v2 95 4.14 crystal oscillator the oscillator of the 71m6543 drives a standard 32.768 khz watch crystal. the oscillator has been designed specifically to handle these crystals and is compatible with thei r high impedance and limited power handling capability. the oscillator power dissipation is very low to maximize the lifet ime of any battery backup device attached to the vbat_rtc pin. board layouts with minimum capacitance from xin to xout require less battery current. good layouts have xin and xout shielded from each other and also keep the xin and xout traces short and away from lcd and digital signals. since the oscillator is self - biasing, an external resistor must not be connected across the crystal. 4.15 meter calibration once the 71m6543 energy meter device has been ins talled in a meter system, it must be calibrated . a complete calibration includes the following: ? establishment of the reference temperature for factory calibratio n (e.g., typically 22 c). ? calibration of the metrology section, i.e. , calibration for errors of the current sensors, voltage di viders and signal conditioning components as well as of the internal reference voltage (vref) at the reference temperature ( e.g. , typically 22 c). ? calibration of the oscillator frequency using the rtc a _adj register ( i/o ram 0x2504 ). the metrology section can be calibrated using the gain and phase adjustment factors accessible to the ce . the gain adjust ment is used to compensate for tolerances of components used for signal condi tioning, especially the resistive componen ts . phase adjustment is provided to compensate for phase shifts introduced by the current sensors or by the effects of reactive power supplies . due to the flexibility of the mpu firmware, any calibration method, such as calibration based on energy, or cur rent and voltage can be implemented . it is also possible to implement segment - wise calibration (de pending on current range). the 71m6543 supports common industry standard calibration techniques, such as s ingle - point (ener gy - only), multi - point (energy, vrms, irms), and auto - calibration. maxim provides a calibration spreadsheet file to facilitate the calibration process . contact your maxim representative to obtain a copy of the latest calibration spreadsheet file for the 71m6543. downloaded from: http:///
71m6543f/71m6543g data sheet 96 v2 5 firmware interface 5.1 i/o ram map C functional order in table 68 and table 69 , unimplemented (u) and reserved (r) bits are shaded in light gray. uni mplemented bits are identified with a u. unimplemented bits have no memory storage, writing them has no effect, and r eading them always returns zero. reserved bits ar e identified with an r, and must always be written with a zero. writing values other t han zero to reserved bits may have undesirable side effects and must be avoided. non - volatile bits are shaded in dark gray. non - volatile bits are backed - up during power failures if the system includes a battery connected to the vbat pin. the i/o ram locati ons listed in table 68 have sequential addresses to facilitate reading by the mpu (e.g., in order to ver ify their contents). these i/o ram locations a re u sually modified only at boot - up . the addresses shown in table 68 are an alternative sequential address to the addresses from table 69 which are used throughout this document. for instance, equ[2:0] can be accessed at i/o ram 0x200 0 [7:5] or at i/o ram 0x2106[7:5] . table 68 : i/o ram map C functional order, basic configuration name addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ce6 2000 equ[2:0] u chop_e[1:0] rtm_e ce_e ce5 2001 u sum_samps[12:8] ce4 2002 sum_samps[7:0] ce3 2003 u ce_lctn[ 6/ 5:0] ce2 2004 pls_maxwidth[7:0] ce1 2005 pls_interval[7:0] ce0 2006 diff6 _e diff4 _e diff2 _e diff0 _e rfly_dis fir_len [1:0] pls_inv rce0 2007 chopr[1:0] rmt6 _e rmt4 _e rmt2 _e tmuxr6 [2:0] rtmux 2008 u tmuxr4 [2:0] u tmuxr2 [2:0] fovrd 2009 u u r u u u u u mux5 200a mux_div[3:0] mux10_sel mux4 200b mux9_sel mux8_sel mux3 200c mux7_sel mux6_sel mux2 200d mux5_sel mux4_sel mux1 200e mux3_sel mux2_sel mux0 200f mux1_sel mux0_sel temp 2010 temp_bsel temp_pwr osc_comp temp_bat tbyte_busy temp_per[2:0] lcd0 2011 lcd_e lcd_mode[2:0] lcd_allcom lcd_y lcd_clk[1:0] lcd1 2012 lcd_vmode[1:0] lcd_blnkmap23[5:0] downloaded from: http:///
71m6543f/71m6543g data sheet v2 97 name addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lcd2 2013 lcd_bat r lcd_blnkmap22[5:0] lcd_map6 2014 lcd_map[55:48] lcd_map5 2015 lcd_map[47:40] lcd_map4 2016 lcd_map[39:32] lcd_map3 2017 lcd_map[31:24] lcd_map2 2018 lcd_map[23:16] lcd_map1 2019 lcd_map[15:8] lcd_map0 201a lcd_map[7:0] dio_r5 201b u u u u u dio_rpb[2:0] dio_r4 201c u dio_r11[2:0] u dio_r10[2:0] dio_r3 201d u dio_r9[2:0] u dio_r8[2:0] dio_r2 201e u dio_r7[2:0] u dio_r6[2:0] dio_r1 201f u dio_r5[2:0] u dio_r4[2:0] dio_r0 2020 u dio_r3[2:0] u dio_r2[2:0] dio0 2021 dio_eex[1:0] u u opt_txe[1:0] opt_txmod opt_txinv dio1 2022 dio_pw dio_pv opt_fdc[1:0] u opt_rxdis opt_rxinv opt_bb dio2 2023 dio_px dio_py u u u u u u int1_e 2024 ex_eex ex_xpulse ex_ypulse ex_rtc t u ex_rtc1m ex_rtc1s ex_xfer int2_e 2025 ex_spi ex_wpulse ex_vpulse wake_e 2026 ew_rx ew_pb ew_dio 4 ew_dio 52 ew_dio 55 sfmm 2080 sfmm[7:0]* sfms 2081 sfms[7:0]* notes: * sfmm and sfms are accessible only through the spi slave port. see 2.5.1.1 flash memory for details. downloaded from: http:///
71m6543f/71m6543g data sheet 98 v2 table 69 lists bits and registers that may have to be accessed on a frequent basis. reserved bits have lighter gray background, and non - volatile bits have a darker gray background. table 69 : i/o ram map C functional order name addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ce and adc mux5 2100 mux_div[3:0] mux10_sel[3:0] mux4 2101 mux9_sel[3:0] mux8_sel[3:0] mux3 2102 mux7_sel[3:0] mux6_sel[3:0] mux2 2103 mux5_sel[3:0] mux4_sel[3:0] mux1 2104 mux3_sel[3:0] mux2_sel[3:0] mux0 2105 mux1_sel[3:0] mux0_sel[3:0] ce6 2106 equ[2:0] u chop_e[1:0] rtm_e ce_e ce5 2107 u sum_samps[12:8] ce4 2108 sum_samps[7:0] ce3 2109 u ce_lctn[ 6 :0] (71m6543g), ce_lctn[5:0] (71m6543f) ce2 210a pls_maxwidth[7:0] ce1 210b pls_interval[7:0] ce0 210c diff6 _e diff4 _e diff2 _e diff0 _e rfly_dis fir_len [1:0] pls_inv rtm0 210d u u u u u u rtm0[9:8] rtm0 210e rtm0[7:0] rtm1 210f rtm1[7:0] rtm2 2110 rtm2[7:0] rtm3 2111 rtm3[7:0] clock generation ckgn 2200 u u adc_div pll_fast reset mpu_div[2:0] vref trim fuses trimt 2309 trimt[7:0] lcd/dio lcd0 2400 lcd_e lcd_mode[2:0] lcd_allcom lcd_y lcd_clk[1:0] lcd1 2401 lcd_vmode[1:0] lcd_blnkmap23[5:0] lcd2 2402 lcd_bat r lcd_blnkmap22[5:0] lcd_map6 2405 lcd_map[55:48] lcd_map5 2406 lcd_map[47:40] lcd_map4 2407 lcd_map[39:32] lcd_map3 2408 lcd_map[31:24] downloaded from: http:///
71m6543f/71m6543g data sheet v2 99 name addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lcd_map2 2409 lcd_map[23:16] lcd_map1 240a lcd_map[15:8] lcd_map0 240b lcd_map[7:0] lcd4 240c u u u u u lcd_rst lcd_blank lcd_on lcd_dac 240d u u u lcd_dac[4:0] segdio0 2410 u u lcd_seg0[5:0] u u segdio15 241f u u lcd_seg15[5:0] segdio16 2420 u u lcd_segdio16[5:0] u u segdio 45 243d u u lcd_segdio45[5:0] segdio 46 243e u u lcd_seg46[5:0] u u segdio 50 2442 u u lcd_seg50[5:0] segdio 51 2443 u u lcd_segdio51[5:0] u u segdio 55 2447 u u lcd_segdio55[5:0] dio_r5 2450 u r r r u dio_rpb[2:0] dio_r4 2451 u dio_r11[2:0] u dio_r10[2:0] dio_r3 2452 u dio_r9[2:0] u dio_r8[2:0] dio_r2 2453 u dio_r7[2:0] u dio_r6[2:0] dio_r1 2454 u dio_r5[2:0] u dio_r4[2:0] dio_r0 2455 u dio_r3[2:0] u dio_r2[2:0] dio0 2456 dio_eex[1:0] u u opt_txe[1:0] opt_txmod opt_txinv dio1 2457 dio_pw dio_pv opt_fdc[1:0] u opt_rxdis opt_rxinv opt_bb dio2 2458 dio_px dio_py u u u u u u nv bits sparenv 2500 u u u u r fovrd 2501 u u r u u u u u tmux 2502 u u tmux[ 5 :0] tmux2 2503 u u u tmux2[4:0] rtc1 2504 u rtca_adj[6:0] 71m6xx3 interface downloaded from: http:///
71m6543f/71m6543g data sheet 100 v2 name addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 remote2 2602 rmt_rd[15:8] remote1 2603 rmt_rd[7:0] rbits int1_e 2700 ex_eex ex_xpulse ex_ypulse ex_rtc t u ex_rtc1m ex_rtc1s ex_xfer int2_e 2701 ex_spi ex_wpulse ex_vpulse u u u u u secure 2702 flsh_unlock[3:0] r flsh_rde flsh_wre r analog0 2704 vref_cal vref_dis pre_e adc_e bcurr spare[2:0] version 2706 version[7:0] intbits 2707 u int6 int5 int4 int3 int2 int1 int0 flag0 sfr e8 ie_eex ie_xpulse ie_ypulse ie_rtc t u ie_rtc1m ie_rtc1s ie_xfer flag1 sfr f8 ie_spi ie_wpulse ie_vpulse u u u u pb_state stat sfr f9 u u u pll_ok u vstat[2:0] remote0 sfr fc u perr_rd perr_wr rcmd[4:0] spi1 sfr fd spi_cmd[7:0] spi0 2708 spi_stat[7:0] rce0 2709 chopr[1:0] rmt6 _e rmt4 _e rmt2 _e tmuxr6 [2:0] rtmux 270a u tmuxr4 [2:0] u tmuxr2 [2:0] dio3 270c u u port_e spi_e spi_safe u u u nv ram and rtc nvramxx 2800 - 287f nvram[0] C nvram[7f] C direct access wake 2880 wake_tmr[7:0] stemp1 2881 stemp[10:3] stemp0 2882 stemp[2:0] u u u u u bsense 2885 bsense[7:0] lkpaddr 2887 lkpautoi lkpaddr[6:0] lkpdata 2888 lkpdat[7:0] lkpctrl 2889 u u u u u u lkp_rd lkp_wr rtc0 2890 rtc_wr rtc_rd u rtc_fail u u u u rtc2 2892 rtc_sbsc[7:0] rtc3 2893 u u rtc_sec[5:0] rtc4 2894 u u rtc_min[5:0] rtc5 2895 u u u rtc_hr[4:0] downloaded from: http:///
71m6543f/71m6543g data sheet v2 101 name addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rtc6 2896 u u u u u rtc_day[2:0] rtc7 2897 u u u rtc_date[4:0] rtc8 2898 u u u u rtc_mo[3:0] rtc9 2899 rtc_yr[7:0] rtc10 289b u u u u u rtc_p[16:14] rtc11 289c rtc_p[13:6] rtc12 289d rtc_p[5:0] rtc_q[1:0] rtc13 289e u u rtc_tmin[5:0] rtc14 289f u u u rtc_thr[4:0] temp 28 a0 temp_bsel temp_pwr osc_comp temp_bat tbyte_busy temp_per[2:0] wf1 28b0 wf_cstart wf_rst wf_rstbit wf_ovf wf_erst wf_badvdd u u wf2 28b1 u u wf_tmr wf_rx wf_pb wf_dio 4 wf_dio 52 wf_dio 55 misc 28b2 sleep lcd_only wake_arm u u u u u wake_e 28b3 u u u ew_rx ew_pb ew_dio 4 ew_dio 52 ew_dio 55 wdrst 28b4 wd_rst temp_start u u u u u u mpu ports port3 sfr b0 dio_dir[15:12] dio[15:12] port2 sfr a0 dio_dir[11:8] dio[11:8] port1 sfr 90 dio_dir[7:4] dio[7:4] port0 sfr 80 dio_dir[3:0] dio[3:0] flash erase sfr 94 flsh_erase[7:0] flshctl sfr b2 preboot secure u u flsh_pend flsh_pstwr flsh_meen flsh_pwe fl_bank sfr b6 u u u u u u fl_bank[1:0] pgadr sfr b7 flsh_pgadr[ 5 :0] u u i 2 c eedata sfr 9e eedata[7:0] eectrl sfr 9f eectrl[7:0] downloaded from: http:///
71m6543f/71m6543g data sheet 102 v2 5.2 i/o ram map C alphabetical order table 70 lists i/o ram bits and registers in alphabetical order. bits with a write direction (w in column dir ) are written by the mpu into configuration ram. typically, they are initially stored in flash memory and copied to the configuration ram by the mpu. some of the more frequently program med bits are mapped to the mpu sfr memory space. the remaining bits are mapped to the address space 0x2xxx. bits with r (read) direc tion can be read by the mpu. columns labeled rst and wk describe the bit values upon reset and wake, respectively. no entry in one of these c olumns means the bit is either read - only or is powered by the nv supply and is not initia lized. write - only bits return zero when they are read. locations that are shaded in grey are non - volatile (i.e., battery - backed) . table 70 : i/o ram map C alphabetical order name location rst wk dir description adc_e 2704[4] 0 0 r/w enables adc and vref. when disabled, reduces bias current . adc_div 2200[5] 0 0 r/w adc_div c ontrols the rate of the adc and fir clocks. the adc_div setting determines whether mck is divided by 4 or 8: 0 = mck/4 1 = mck/8 the resulting adc and fir clock is as shown below. pll_fast = 0 pll_fast = 1 mck 6.291456 mhz 19.660800 mhz adc_div = 0 1.572864 mhz 4.9152 mhz adc_div = 1 0.786432 mhz 2.4576 mhz bcurr 2704[3] 0 0 r/w connects a 100 a load to the battery selected by temp_bsel . bsense[7:0] 2885[7:0] C C r the result of the battery measurement. see 2.5.7 71m6543 battery monitor on page 56 . ce_e 2106[0] 0 0 r/w ce enable. ce_lctn[ 6 :0] 2109[ 6 :0] 31 31 r/w ce program location. the starting address for the ce program is 1024* ce_lctn . ( ce_lctn[6:0] , 2109[6:0] for 71m6543g) ( ce_lctn[5:0] , 2109[5:0] for 71m6543f) chip_id[15:8] chip_id[7:0] 2300[7:0] 2301[7:0] 0 0 0 0 r r these bytes contain the chip identification as shown below . chip_id[15:8] chip_id[7:0 ] 71m6543f 0x04 0x10 71m6543 g 0x05 0x10 chop_e[1:0] 2106[3:2] 0 0 r/w chop enable for the reference bandgap circuit. the value of chop change s on the rising edge of the internal muxsync signal according to the value in chop_e[1:0] : 00 = toggle 1 01 = positive 10 = reversed 11 = toggle 1 except at the mux sync edge at the end of an accumulation interval . downloaded from: http:///
71m6543f/71m6543g data sheet v2 103 name location rst wk dir description chopr[1:0] 2709[7:6] 00 00 r/w the chop settings for the remote sensor. 00 = auto chop. change every mux frame. 01 = positive 10 = negative 11 = auto chop (same as 00 ) diff0 _e 210c[4] 0 0 r/w enables iadc0 - iadc1 differential configuration. diff2 _e 210c[5] 0 0 r/w enables iadc2 - iadc3 differential configuration. diff4 _e 210c[6] 0 0 r/w enables iadc4 - iadc5 differential configuration. diff6 _e 210c[7] 0 0 r/w enables iadc6 - iadc7 differential configuration. dio_r2[2:0] dio_r3[2:0] dio_r4[2:0] dio_r5[2:0] dio_r6[2:0] dio_r7[2:0] dio_r8[2:0] dio_r9[2:0] dio_r10[2:0] dio_r11[2:0] dio_rpb[2:0] 2455[2:0] 2455[6:4] 2454[2:0] 2454[6:4] 2453[2:0] 2453[6:4] 2452[2:0] 2452[6:4] 2451[2:0] 2451[6:4] 2450[2:0] 0 0 0 0 0 0 0 0 0 0 0 C r/w connects pb and dedicated i/o pins dio2 through dio11 to internal resources . if more than one input is connected to the same resource, the multiple column below specifies how they are combined. dio_rx resource multiple 0 none C 1 reserved or 2 t0 (timer0 clock or gate) or 3 t1 (timer1 clock or gate) or 4 io interrupt (int0) or 5 io interrupt (int1) or dio_dir[15:12] dio_dir[11:8] dio_dir[7:4] dio_dir[3:0] sfr b0[7:4] sfr a0[7:4] sfr 90[7:4] sfr 80[7:4] f f r/w programs the direction of the first 16 dio pins. 1 indicates output. ignor ed if the pin is not configured as i/o. see dio_pv and dio_pw for special option for dio0 and dio1 outputs. see dio_eex [1:0] for special option for seg dio2 and s eg dio3. note that the direction of dio pins above 15 is set by segdiox[1] . see port_e to avoid power - up spikes. dio[15:12] dio[11:8] dio[7:4] dio[3:0] sfr b0[3:0] sfr a0[3:0] sfr 90[3:0] sfr 80[3:0] f f r/w the value on the first 16 dio pins. pins configured as lcd read zero. when written, changes data on pins configured as outputs. pins configured as lcd or input ignore writes. note that the data for dio pins above 15 is set by segdiox[0] . downloaded from: http:///
71m6543f/71m6543g data sheet 104 v2 name location rst wk dir description dio_eex[1:0] 2456[7:6] 0 C r/w when set, converts seg dio3 and seg dio2 to interface with external eeprom. segdio2 becomes sdck and segdio3 becomes bi - directional sdata, but only if lcd_map[2] and lcd_map[3] are cleared. dio_eex[1:0] function 00 disable eeprom interface 01 2- wire eeprom interface 10 3- wire eeprom interface 11 3- wire eeprom interface with separate do ( seg dio3) and di ( seg dio8) pins. dio_pv 2457[6] 0 C r/w causes vpulse to be output on seg dio1, if lcd_map[1] =0. dio_pw 2457[7] 0 C r/w causes wpulse to be output on seg dio0, if lcd_map[0]= 0. dio_px 2458[7] 0 C r/w causes xpulse to be output on seg dio6 , if lcd_map[6]= 0. dio_py 2458[6] 0 C r/w causes ypulse to be output on seg dio7 , if lcd_map[7]= 0. eedata[7:0] sfr 9e 0 0 r/w serial eeprom interface data . eectrl[7:0] sfr 9f 0 0 r/w serial eeprom interface control . status bit name read/ write reset state polarity description 7 error r 0 positive 1 when an illegal command is received. 6 busy r 0 positive 1 when serial data bus is busy. 5 rx_ack r 1 positive 1 indicates that the eeprom sent an ack bit. equ[2:0] 2106[7:5] 0 0 r/w specifies the power equation. equ[2:0] description element 0 element 1 element 2 recommended mux sequence 3 2 element, 4w, 3 del ta va(i a- ib)/ 2 0 vc ic ia va ib i c vc 4 2 element, 4w, 3 wye va(ia - ib)/2 vb(ic - ib)/2 0 ia va ib v b i c 5* 3 element, 4w, 3 w ye va ia vb ib vc ic ia v a ib vb ic vc note: *the available ce codes implements only equ a tion 5. co n tact your local maxim representative to obtain ce co de for equation 3 and 4. downloaded from: http:///
71m6543f/71m6543g data sheet v2 105 name location rst wk dir description ex_xfer ex_rtc1s ex_rtc1m ex_rtct ex_spi ex_eex ex_xpulse ex_ypulse ex_wpulse e x_vpulse 2700[0] 2700[1] 2700[2] 2700[3] 2701[7] 2700[7] 2700[6] 2700[5] 2701[6] 2701[5] 0 0 r/w interrupt enable bits. these bits enable the xfer_busy, the rtc_1sec, e tc. the bits are set by hardware and cannot be set by writing a 1. the bits are reset by writing 0. note that if one of these interrupts is to enabled, its corresponding 8051 ex ena ble bit must also be set. see 2.4.8 interrupts , for details . ew_dio4 28b3[2] 0 C r/w connects seg dio4 to the wake logic and permits seg dio4 rising to wake the part. this bit has no effect unless dio4 is configured as a digital input. ew_dio52 28b3[1] 0 C r/w connects seg dio52 to the wake logic and permits seg dio52 rising to wake the part. this bit has no effect unless seg dio52 is configured as a digital input. ew_dio55 28b3[0] 0 C r/w connects seg dio55 to the wake logic and permits the seg dio55 rising edge to awaken the part. this bit has no effect unless seg dio55 is configured as a digital input. ew_pb 28b3[3] 0 C r/w connects pb to the wake logic and permits a high level on pb to a wake n the part. pb is always configured as an input. ew_rx 28b3[4] 0 C r/w connects rx to the wake logic and permits the rx rising edge to a wake n the part. see the wake description in 3.4 wake on timer for de - bounce issues. fir_len [1:0] 210c[2:1] 0 0 r/w determines t he number of adc cycles in the adc decimation fir filter. pll_fast = 1: fir_len[1:0] adc cycles 00 141 01 288 10 384 pll_fast = 0: fir_len[1:0] adc cycles 00 135 01 276 10 not allowed the adc lsb size and full - scale values depend on the fir_len[1:0] setting. refer to table 81 on page 122 and table 103 on page 141 for details. downloaded from: http:///
71m6543f/71m6543g data sheet 106 v2 name location rst wk dir description fl_bank[1:0] sfr b6[1:0] 01 01 r/w flash bank selection (71m6543g only) the program memory of the 71m6543g consists of a fixed lower bank of 32 kb, addressable at 0x0000 to 0x7fff plus an upper banked area of 32 kb, addressable at 0x8000 to 0xffff. the i/o ram register fl_bank is used to switch one of four memory banks of 32 kb each into the address range from 0x8000 to 0xffff. not e that when fl_bank = 0, the upper bank is the same as the lower bank. fl_bank[1:0] address range for lower bank (0x0000 - 0x7fff) address range for upper bank (0x8000 - 0xffff) 00 0x0000 - 0x7fff 0x0000 - 0x7fff 01 0x0000 - 0x7fff 0x8000 - 0xffff 10 0x0000 - 0x7fff 0x10000 - 0x17fff 11 0x0000 - 0x7fff 0x18000 - 0x1ffff flsh_erase[7:0] sfr 94[7:0] 0 0 w flash erase initiate flsh_erase is used to initiate either the flash mass erase cycle or the flash pa ge erase cycle. specific patterns are expected for flsh_erase in order to initiate the appropriate erase cycle. (default = 0x00). 0x55 C initiate flash page erase cycle. must be proceeded by a write to flsh_pgadr [5 :0] ( sfr 0xb7 ). 0xaa C initiate flash mass erase cycle. must be proceeded by a write to flsh_meen ( sfr 0xb2 ) and the debug (cc) port must be enabled. any other pattern written to flsh_erase ha s no effect. flsh_meen sfr b2[1] 0 0 w mass erase enable 0 = mass erase disabled (default). 1 = mass erase enabled. must be re - written for each new mass erase cycle . flsh_pend sfr b2[3] 0 0 r indicates that a posted flash write is pending. if another flash wri te is attempted, it is ignored. flsh_pgadr[ 5 :0] sfr b7[7: 2] 0 0 w flash page erase address flash page address (page 0 thru 63) that is erased during the page erase cycle. (default = 0x00). must be re - written for each new page erase cycle. flsh_pstwr sfr b2[2] 0 0 r/w enables posted flash writes. when 1, and if ce_e = 1, flash write requests are stored in a one element deep fifo and are executed when ce_busy falls. flsh_pend can be read to determine the status of the fifo. if flsh_pstwr = 0 or if ce_e = 0, flash writes are immediate. downloaded from: http:///
71m6543f/71m6543g data sheet v2 107 name location rst wk dir description flsh_pwe sfr b2[0] 0 0 r/w program write enable 0 = movx commands refer to external ram space, normal operation (default ). 1 = movx @ dptr ,a moves a to external program space (flash) @ dptr . this bit is automatically reset after each byte written to flash. w rites to this bit are inh ibited when interrupts are enabled. flsh_rde 2702[2] C C r indicates that the flash may be read by ice or spi slave. flsh_rde = (! secure ) flsh_unlock[3:0] 2702[7:4] 0 0 r/w must be a 2 to enable any flash modification. see the description of flash se curity for more details. flsh_wre 2702[1] C C r indicates that the flash may be written through ice or spi slave port s. ie_xfer ie_rtc1s ie_rtc1m ie_rtc t ie_spi ie_eex ie_xpulse ie_ypulse ie_wpulse ie_vpulse sfr e8[0] sfr e8[1] sfr e8[2] sfr e8[3] sfr f8[7] sfr e8[7] sfr e8[6] sfr e8[5] sfr f8[ 6] sfr f8[ 5] 0 0 r/w interrupt flags for external interrupts 2 and 6. these flags monitor the source of the int6 and int2 interrupts (external interrupts to the mpu core). the se flags are set by hardware and must be cleared by the software interrupt handler. the iex2 ( sfr 0xc0[1] ) and iex6 ( sfr 0xc0[5] ) interrupt flags are automatically cleared by the mpu core when it vectors to the interrupt handler. iex2 and iex6 must be cleared by writing zero to their corresponding bit positions in sfr 0xc0, while writing ones to the other bit positions that are not being cleared. intbits 2707[6:0] C C r interrupt inputs. the mpu may read these bits to see the input to external in terrupts int0, int1, up to int6. these bits do not have any memory and are primari ly intended for debug use. lcd_allcom 2400[3] 0 C r/w configures seg/com bits as com. has no effect on pins whose lcd_map bit is zero. lcd_bat 2402[7] 0 C r/w connects the lcd power supply to vbat in all modes. lcd_blnkmap23[5:0] lcd_blnkmap22[5:0] 2401[5:0] 2402[5:0] 0 C r/w identifies which segments connected to seg23 and seg22 should blink. 1 means blink. the most significant bit corresponds to com5, the least significant, to com0. lcd_clk[1:0] 2400[1:0] 0 C r/w sets the lcd clock frequency. note: f xtal = 32768 hz lcd_clk[1:0] lcd clock frequency 00 f xtal /2 9 01 f xtal /2 8 10 f xtal /2 7 11 f xtal /2 6 downloaded from: http:///
71m6543f/71m6543g data sheet 108 v2 name location rst wk dir description lcd_dac[4:0] 240d[4:0] 0 C r/w the lcd contrast dac. this dac controls the vlcd voltage and has an output range of 2. 65 v to 5 .3 v . the vlcd voltage is vlcd = 2. 6 5 + 2. 6 5 * lcd_dac[4:0]/ 31 thus, the lsb of the dac is 85.5 mv. the maximum dac output voltage is limited by v3p3sys, vbat, and whether lcd_bste = 1. lcd_e 2400[7] 0 C r/w enables the lcd display. when disabled, vlc2, vlc1, and vlc0 are ground as are the com and seg outputs if their lcd_map bit is 1. lcd_map[55:48] lcd_map[47:40] lcd_map[39:32] lcd_map[31:24] lcd_map[23:16] lcd_map[15:8] lcd_map[7:0] 2405[7:0] 2406[7:0] 2407[7:0] 2408[7:0] 2409[7:0] 240a[7:0] 240b[7:0] 0 0 0 0 0 0 0 C C C C C C C r/w r/w r/w r/w r/w r/w r/w enables lcd segment driver mode of combined segdio pins. pins that cannot be configured as outputs (seg48 through seg50) become inputs with internal pull ups when their lcd_map bit is zero. also, note that seg48 through seg50 are multiplexed with the in - circuit emulator signals. when the ice_e pin is high, the ice interface is enabled, and seg48 through seg50 become e_rxtx, e_tclk and e_rst, respectively. lcd_mode[2:0] 2400[6:4] 0 C r/w selects t he lcd bias and multiplex mode. lcd_mode output 000 4 states, 1/3 bias 001 3 states, 1/3 bias 010 2 states, 1/2 bias 011 3 states, 1/2 bias 100 static display 101 5 states, 1/3 bias 110 6 states, 1/3 bias lcd_on lcd_blank 240c[0] 240c[1] 0 0 C C r/w r/w turns on or off all lcd segments without changing lcd data. if both bits are set, the lcd display is turned on. lcd_only 28b2[6] 0 0 w puts the 71m6543 to sleep, but with lcd display still active. ignored if system power is pr esent. it awakens when the wake t imer times out, when certain dio pins are raised, or when system power returns (s ee 3.2 battery mo des ). lcd_rst 240c[2] 0 C r/w clear all bits of lcd data. these bits affect segdio pins that are conf igured as lcd drivers. this bit does not auto clear. lcd_seg0[5:0] to lcd_seg15[5:0] 2410[5:0] to 241f[5:0] 0 C r/w seg data for seg0 through seg15. dio data for these pins is in sf r space. lcd_segdio16[5:0] to lcd_segdio45[5:0] 2420[5:0] to 243d[5:0] 0 C r/w seg and dio data for segdio16 through segdio45. if configured as dio, bit 1 is direction (1 is output, 0 is input), bit 0 is data, and the other bits are ig nored. downloaded from: http:///
71m6543f/71m6543g data sheet v2 109 name location rst wk dir description lcd_seg46[5:0] to lcd_seg50[5:0] 243e[5:0] to 2442[5:0] 0 C r/w seg data for seg46 through seg50. these pins cannot be configured as dio. lcd_segdio51[5:0] to lcd_segdio55[5:0] 2443[5:0] to 2447[5:0] 0 C r/w seg and dio data for segdio51 through segdio55. if configured as dio, bit 1 is direction (1 is output, 0 is input), bit 0 is data, and the other bits are ig nored. lcd_vmode[1:0] 2401[7:6] 00 00 r/w specifies how vlcd is generated. see 2.5.10.3 for the definition of v3p3l. lcd_vmode description 11 external vlcd 10 lcd boost and lcd dac enabled 01 lcd dac enabled 00 no boost and no dac. vlcd=v3p3l. lcd_y 2400[2] 0 C r/w lcd blink frequency (ignored if blink is disabled). 1 = 1 hz , 0 = 0.5 hz lkpaddr[6:0] 2887[6:0] 0 0 r/w the address for reading and writing the rtc lookup ram . lkpautoi 2887[7] 0 0 r/w auto - increment flag. when set, lkpaddr [6:0] auto increment s every time lkp_rd or lkp_wr is pulsed. the incremented address can be read at lkpaddr. lkpdat[7:0] 2888[7:0] 0 0 r/w the data for reading and writing the rtc lookup ram. lkp_rd lkp_wr 2889[1] 2889[0] 0 0 0 0 r/w r/w strobe bits for the rtc lookup ram read and write. when set, the lkpaddr [6:0] and lkpdat registers is used in a read or write operation. when a strobe is set, it stay s set until the operation completes, at which time the strobe is cleared and lkpaddr [6:0 ] is incremented if lkpautoi is set. mpu_div[2:0] 2200[2:0] 0 0 r/w mpu clock rate is: mpu rate = mck rate * 2 - (2+ mpu_div [2:0]) . the maximum value for mpu_div[2:0] is 4. based on the default values of the pll_fast bit and mpu_div[ 2:0 ] , the power - up mpu rate is 6.29 mhz / 4 = 1. 5725 mhz. the minimum mpu clock rate is 38.4 khz when pll_fast = 1. mux0_sel[3:0] 2105[3:0] 0 0 r/w selects which adc input is to be converted during time slot 0. mux1_sel[3:0] 2105[7:4] 0 0 r/w selects which adc input is to be converted during time slot 1. mux2_sel[3:0] 2104[3:0] 0 0 r/w selects which adc input is to be converted during time slot 2. mux3_sel[3:0] 2104[7:4] 0 0 r/w selects which adc input is to be converted during time slot 3. mux4_sel[3:0] 2103[3:0] 0 0 r/w selects which adc input is to be converted during time slot 4. mux5_sel[3:0] 2103[7:4] 0 0 r/w selects which adc input is to be converted during time slot 5. mux6_sel[3:0] 2102[3:0] 0 0 r/w selects which adc input is to be converted during time slot 6. mux7_sel[3:0] 2102[7:4 ] 0 0 r/w selects which adc input is to be converted during time slot 7. downloaded from: http:///
71m6543f/71m6543g data sheet 110 v2 name location rst wk dir description mux8_sel[3:0] 2101[3:0] 0 0 r/w selects which adc input is to be converted during time slot 8. mux9_sel[3:0] 2101[7:4 ] 0 0 r/w selects which adc input is to be converted during time slot 9. mux10_sel[3:0] 2100[3:0] 0 0 r/w selects which adc input is to be converted during time slot 10. mux_div[3:0] 2100[7:4] 0 0 r/w mux_div[3:0] is the number of adc time slots in each mux frame. the maximum number of time slots is 11. opt_bb 2457[0] 0 C r/w configures the input of the optical port to be a dio pin to allow it to be bit - banged. in this case, dio5 becomes a third high speed uart. refer to 2.5.9 uart and optical interface =under the bit banged optical uart (third uart ) sub - heading on page 56 . opt_fdc[1:0] 2457[5:4] 0 C r/w selects opt_tx modulation duty cycle opt_fdc function 00 50% low 01 25% low 10 12.5% low 11 6.25% low opt_rxdis 2457[2] 0 C r/w opt_rx can be configured as an input to the optical uart or as segdio55. opt_rxdis = 0 and lcd_map[55] = 0: opt_rx opt_rxdis = 1 and lcd_map[55] = 0: dio55 opt_rxdis = 0 and lcd_map[55] = 1: seg55 opt_rxdis = 1 and lcd_map[55] = 1: seg55 opt_rxinv 2457[1] 0 C r/w inverts result from opt_rx comparator when 1. affects only the uart input. has no effect when opt_rx is used as a dio input. opt_txe [1,0] 2456[3:2] 00 C r/w configures the opt_tx output pin. if lcd_map[51] = 0: 00 = dio51, 01 = opt_tx, 10 = wpulse, 11 = vpulse if lcd_map[51] = 1: xx = seg51 opt_txinv 2456[0] 0 C r/w invert opt_tx when 1. this inversion occurs before modulation. opt_txmod 2456[1] 0 C r/w enables modulation of opt_tx. when opt_txmod is set, opt_tx is modulated when it would otherwise have been zero. the modulation is applied after any inversion caused by opt_txinv . osc_comp 28a0[5] 0 C r/w enables the automatic update of rtc_p [16:0] and rtc_q [1:0] every time the temperature is measured. pb_state sfr f8[0] 0 0 r the de - bounced state of the pb pin. perr_rd perr_wr sfr fc[6] sfr fc[5] 0 0 r/w the 71m6543 sets these bits to indicate that a parity error on the remote sensor has been detected. once set, the bits are remembered until they are cleared by the mpu. downloaded from: http:///
71m6543f/71m6543g data sheet v2 111 name location rst wk dir description pll_ok sfr f9[4] 0 0 r indicates that the clock generation pll is settled. pll_fast 2200[4] 0 0 r/w controls the speed of the pll and mck. 1 = 19.66 mhz (xtal * 600) 0 = 6.29 mhz (xtal * 192 ) pls_maxwidth[7:0] 210a[7:0] ff ff r/w pls_maxwidth[7:0] d etermines the maximum width of the pulse (low - going pulse if pls_inv =0 or high - going pulse if pls_inv =1 ). the m aximum pulse width is (2* pls_maxwidth [7:0] + 1)*t i . where t i is pls_interval [7:0] in units of ck_fir clock cycles. if pls_interval [7:0] = 0 or pls_maxwidth [7:0] = 255, no pulse width checking is performed and the output pulses have 50% duty cycle. see 2.3.6.2 vpulse and wpulse . pls_interval[7:0] 210b[7:0] 0 0 r/w pls_interval[7:0] d etermines the i nterval time between pulses. the time between output pulses is pls_interval [7:0] *4 in units of ck_fir clock cycles . if pls_interval [7:0] = 0, the fifo is not used and pulses are output as soon as the ce issues t hem. pls_interval[7:0] is calculated as follows: pls_interval[7:0] = f loor ( mux frame duration in ck_fir cycles / ce pulse updates per mux frame / 4 ) for example, since the 71m6543 ce code is written to generate 6 pulses in one integration interval, w he n the fifo is enabled (i.e., pls_interval [7:0] 0) and that the frame duration is 1950 ck_fir clock cycles, pls_interval[7:0] should be written with floor(1950 / 6 / 4) = 81 so that the five pulses are evenly spaced in time over the integration interval and the last pulse is issued just prior to the end of the interval . see 2.3.6.2 vpulse and wpulse . pls_inv 210c[0] 0 0 r/w inverts the polarity of wpulse , varpulse , xpulse, and ypulse . normally, these pulses are active low. when inverted, they become active high. port_e 270c[5] 0 0 r/w enables outputs from the segdio0 - segdio15 pins. port_e = 0 blocks the momentary output pulse that occurs when seg dio0 - seg dio15 are reset on power - up . pre_e 2704[5] 0 0 r/w enables the 8x pre - amp lifier . preboot sfrb2[7] C C r indicates that pre - boot sequence is active. rcmd[4:0] sfr fc[4:0] 0 0 r/w when the mpu writes a non - zero value to rcmd , the 71m6543 issues a command to the appropriate remote sensor. when the command is complete, the 71m6543 clears rcmd. reset 2200[3] 0 0 w when set, writes a one to wf_rstbit and then causes a reset. rfly_dis 210c[3] 0 0 r/w controls how the 71m6543 drives the power pulse for the 71m6xxx. when set, the power pulse is driven high and low. when cleared, it is driven high fol lowed by an open circuit fly - back interval. downloaded from: http:///
71m6543f/71m6543g data sheet 112 v2 name location rst wk dir description rmt2 _e rmt4 _e rmt6 _e 2709[3] 2709[4] 2709[5] 0 0 r/w enables the remote interface. rmt_rd[15:8] rmt_rd[7:0] 2602[7:0] 2603[7:0] 0 0 r response from remote read request. rtc a _adj[6:0] 2504 [6:0] 40 C r/w register for analog rtc frequency adjust ment . rtc_fail 2890[4] 0 0 r indicates that a count error has occurred in the rtc and that the time is not trustworthy. this b it can be cleared by writing a 0 . rtc_p[16:14] rtc_p[13:6] rtc_p[5:0] 289b[2:0] 289c[7:0] 289d[7:2] 4 0 0 4 0 0 r/w rtc adjust. see 2.5.4 real - time clock (rtc) . 0x0ffbf rtc_p 0x10040 note: rtc_p[16:0] and rtc_q[1:0] for m a single 19 - bit rtc adjustment value. rtc_q[1:0] 289d[1:0] 0 0 r/w rtc adjust. see 2.5.4 real - time clock (rtc) . note: rtc_p[16:0] and rtc_q[1:0] form a single 19 - bit rtc adjustment value. rtc_rd 2890[6] 0 0 r/w freezes the rtc shadow register so it is suitable for mpu reads. when rtc_rd is read, it returns the status of the shadow register: 0 = up to date, 1 = frozen. rtc_sbsc[7:0] 2892[7:0] C C r time remaining since the last 1 second boundary. lsb=1/128 second. rtc_tmin[5:0] 289e[5:0] 0 C r/w the target minutes register. see rtc_thr below . rtc_thr[4:0] 289f[4:0] 0 C r/w the target hours register. the rtc_t interrupt occur s when rtc_min [5:0] becomes equal to rtc_tmin[5:0] and rtc_hr[4:0] becomes equal to rtc_thr[4:0] . rtc_wr 2890[7] 0 0 r/w freezes the rtc shadow register so it is suitable for mpu writes. when rtc_wr is cleared, the contents of the shadow register are written to the rtc counter on the next rtc clock (~1 khz). when rtc_wr is read, it return s 1 as long as rtc_wr is set. it c ontinue s to return one until the rtc counter actually updates. rtc_sec[5:0] rtc_min[5:0] rtc_hr[4:0] rtc_day[2:0] rtc_date[4:0] rtc_mo[3:0] rtc_yr[7:0] 2893[5:0] 2894[5:0] 2895[4:0] 2896[2:0] 2897[4:0] 2898[3:0] 2899[7:0] C C C C C C C C C C C C C C r/w the rtc interface. these are the year, month, day, hour, minute and second parameters for the rtc. the rtc is set by writing to these registers. year 00 and all others divisible by 4 are defined as a leap year. sec 00 to 59 min 00 to 59 hr 00 to 2 3 (00=midnight) day 01 to 07 (01=sunday) date 01 to 31 mo 01 to 12 yr 00 to 99 each write operation to one of these registers must be preceded by a write to 0x 2 890 . rtm_e 2106[1] 0 0 r/w real time monitor enable. when 0, the rtm output is low. downloaded from: http:///
71m6543f/71m6543g data sheet v2 113 name location rst wk dir description rtm0[9:8] rtm0[7:0] rtm1[7:0] rtm2[7:0] rtm3[7:0] 210d[1:0] 210e[7:0] 210f[7:0] 2110[7:0] 2111[7:0] 0 0 0 0 0 0 0 0 0 0 r/w four rtm probes. before each ce code pass, the values of these registers are s erially output on the rtm pin. the rtm registers are ignored when rtm_e = 0. note that rtm0 is 10 bits wide. the others assume the upper two bits are 00. secure sfr b2[6] 0 0 r/w inhibits erasure of page 0 and flash memory addresses above the beginning of ce code as defined by ce_lctn[ 6/ 5:0]. also inhibits the reading of flash memory by ex ternal devices (spi or ice port). sleep 28b2[7] 0 0 w puts the 71m6543 to sleep. ignored if system power is present. the 71m6543 wake s when the wake timer times out, when push button is pushed, or when system power returns. spi_cmd sfr fd[7:0] C C r spi command. 8- bit command from the bus master. spi_e 270c[4] 1 1 r/w spi port enable. enables the spi interface on pins seg dio 36 C seg dio 39. requires that lcd_map[36 - 39] = 0. spi_safe 270c[3] 0 0 r/w l imits spi writes to spi_cmd and a 16 byte region in dram. no other writes are per mitted. spi_stat 2708[7:0] 0 0 r spi_stat contains the status results from the previous spi transaction bit 7 - 71m6543 ready error: the 71m6543 was not ready to read or write as directed by the previous command. bit 6 - read data parity: this bit is the parity of all bytes read from t he 71m6543 in the previous command. does not include the spi_stat byte. bit 5 - write data par ity: this bit is the overall parity of the bytes written to the 71m6543 in the previous command. i t includes cmd and addr bytes. bit 4:2 - bottom 3 bits of the byte count. does not in clude addr and cmd bytes. one, two, and three byte instructions return 111. bit 1 - spi flash mode: this bit is zero when the test pin is zero. bit 0 - spi flash mode ready: used in spi flash mode. indicates that the flash is ready to receive another write instruction. stemp[10:3] stemp[2:0] 2881[7:0] 2882[7:5] C C C C r r the result of the temperature measurement. sum_samps[12:8] sum_samps[7:0] 2107[4:0] 2108[7:0] 0 0 r/w the number of multiplexer cycles (frames) per xfer_busy interrupt. maxim um value is 8191 cycles. tbyte_busy 28a0[3] 0 0 r indicates that hardware is still writing the 0x 28a0 byte. additional writes to this byte are locked out while it is one. write duration could be as long as 6 ms. temp_22[10:8] temp_22[7:0] 230a[2:0] 230b[7:0] 0 C r storage location for stemp [10:0] at 22c. stemp [10:0] is an 11 bit word. downloaded from: http:///
71m6543f/71m6543g data sheet 114 v2 name location rst wk dir description temp_bat 28a0[4] 0 C r/w causes vbat to be measured whenever a temperature measurement is per formed. temp_bsel 28a0[7 ] 0 C r/w selects which battery is monitored by the temp erature sensor: 1 = vbat, 0 = vbat_rtc temp_per[2:0] 28a0[2:0] 0 C r/w sets the period between temperature measurements. automatic measurements can be enabled in any mode (msn, brn, lcd, or slp). temp_per = 0 disables automatic temperature updates, in which case temp_start may be used by the mpu to initiate a one - shot temperature measurement. temp_per time (seconds) 0 no temperature updates 1-6 ) per _ temp 3( 2 + 7 continuous updates temp_pwr 28a0[6 ] 0 C r/w selects the power source for the temp sensor: 1 = v3p3d, 0 = vbat_rtc. this bit is ignored in slp and lcd modes, where the temp sensor is always p owered by vbat_rtc. temp_start 28b4[6] 0 0 r/w when temp_per = 0 automatic temperature measurements are disabled, and temp_start may be set by the mpu to initiate a one - shot temperature measurement. temp_start is i gnored in slp and lcd modes. hardware clears temp_start when the temperature measurement is complete. tmux[ 5 :0] 2502[5 :0] C C r/w selects one of 32 signals for tmuxout. see 2.5.14 for details. tmux2[ 4 :0] 2503[4:0] C C r/w selects one of 32 signals for tmux2out. see 2.5.14 for details. tmuxr2 [2:0] tmuxr4 [2:0] tmuxr6 [2:0] 270a[2:0] 270a[6:4] 2709[2:0] 000 000 r/w the tmux setting for the remote isolated sensors (71m6xx 3 ). version[7:0] 2706[7:0] C C r the silicon version index. this word may be read by firmware to deter mine the silicon version. version[7:0] 71m6543f silicon version 71m6543g silicon version 0001 0001 a01 a01 0001 001 1 a03 n/a 0001 001 1 b01 n/a 0010 0010 b02 n/a vref_cal 2704[7] 0 0 r/w brings the adc reference voltage out to the vref pin. this feature is di sabled when vref_dis =1. vref_dis 2704[6] 0 1 r/w disables the internal adc voltage reference. downloaded from: http:///
71m6543f/71m6543g data sheet v2 115 name location rst wk dir description vstat[2:0] sfr f9[2:0] C C r this word describes the source of power and the status of the vdd. vstat[2:0] description 000 system power ok. v3p3a>3.0v. analog modules are functional and accurate. [v3aok,v3ok]=11 001 system power low. 2.8v2.25v. full digital functional ity. [v3aok,v3ok]=00 , [vddok,vddgt2]=11 011 battery power and vdd>2.0. flash writes are inhibited. if the trimvdd[5] fuse is blown, pll_fast is cleared. [v3aok,v3ok]=00 , [vddok,vddgt2]=01 101 battery power and vdd<2.0. when vstat=101, processor is nearly out of voltage. processor failure is imminent. [v3aok,v3ok]=00 , [vddok,vddgt2]=00 wake_arm 28b2[5] 0 C r/w arms the wake timer and loads it with wake_tmr[7:0]. when sleep or lcd mode is asserted by the mpu, the wake timer become s active. wake_tmr 2880[7:0] 0 C r/w timer duration is wake_tmr+1 seconds. wd_rst 28b4[7] 0 0 w reset the wd timer. the wd is reset when a 1 is written to this b it. writing a one clears and restarts the watch dog timer. wf_dio4 28b1[2] 0 C r dio4 wake flag bit. if dio4 is configured to wake the part, this bit is set whenever the de - bounced version of dio4 rises. it is held in reset if di04 is not configured f or wakeup. wf_dio52 28b1[1] 0 C r dio52 wake flag bit. if dio52 is configured to wake the part, this bit i s set whenever the de - bounced version of dio52 rises. it is held in reset if di052 is not configured for wakeup. wf_dio55 28b1[0] 0 C r dio55 wake flag bit. if dio55 is configured to wake the part, this bit i s set whenever the de - bounced version of dio55 rises. it is held in reset if di055 is not configured for wakeup. wf_tmr 28b1[5] 0 C r indicates that the wake timer caused the part to wake up. wf_pb 28b1[3] 0 C r indicates that the pb caused the part to wake. wf_rx 28b1[4] 0 C r indicates that rx caused the part to wake. wf_cstart wf_rst wf_rstbit wf_ovf wf_erst wf_badvdd 28b0[7] 28b0[6] 28b0[5] 28b0[4] 28b0[3] 28b0[2] 0 1 0 0 0 0 C r indicates that the reset pin, reset bit, erst pin, watchdog timer , the cold start detector , or bad vbat caused the part to reset. downloaded from: http:///
71m6543f/71m6543g data sheet 116 v2 5.3 ce interface description 5.3.1 ce program the ce performs the precision computations necessary to accurately measure po wer. these computa tions include offset cancellation, phase compensation, product smoothing, product summation, fr equency de tection, var calculation, sag detec tion and voltage phase measurement. all data computed by the ce is dependent on the selected meter equation as given by equ[2:0] ( i/o ram 0x2106[7:5] ). the standard ce program is supplied by maxim as a data image that can be merged with the mpu op erational code for meter applications . typically, this ce program covers most applications and does not need to be modified . other variations of ce code may be available from maxim . the description in this section applies to ce code revision ce43 a01a . 5.3.2 ce data format all ce words are 4 bytes . unless specified otherwise, they are in 32 - bit twos complement format (- 1 = 0xffffffff) . calibration para meters are defined in flash memory (or external eeprom) and must be copied to ce data memory by the mpu before enabling the ce . internal variables are used in int ernal ce calculations . input variables allow the mpu to control the behavior of the ce code . output variables are outputs of the ce calculations . the corresponding mpu address for the most signi ficant byte is given by 0x0000 + 4 x ce_address and by 0x0 003 + 4 x ce_address for the least significant byte. 5.3.3 constants constants used in the ce data memory tables are: ? sampling frequency: f s = 32768 hz/15 = 2184.53 hz. ? f 0 is the fundamental frequency of the mains phases . ? imax is the external rms current corresponding to 250 mv pk at each iadc input . ? vmax is the external rms voltage corresponding to 250 mv pk at each vadc input. ? n acc , the accumulation count for energy measurements is sum_samp s [12:0] (i/o ram 0x2107[4:0], 0x2108[7:0]) . this value also resides in sum_pre ( ce ram 0x23 ) where it is used for phase angle measurement. ? the duration of the accumulation interval for energy measurements is sum_samps[12:0] /f s . ? x is a gain constant of the pulse generators. its value is determined by pulse_fast and pulse_slow (see table 76 ) . ? voltage lsb = vmax * 7.879810 - 9 v. ? vmax = 600 v, imax = 208 a, and kh = 3.2 wh/pulse are assumed as default s ettings. the system constants imax and vmax are used by the mpu to convert internal digital quantities (as used by the ce) to external, i.e. metering quantities. their values are determined by the scaling of the voltage and current sensors used in an actual meter. the lsb values used in this document relate digital quantities at the ce or mpu interface to external meter input quantities. for example, if a sag threshold of 80 v peak is desired at the meter input, the digital value that should be progr ammed into sa g_thr (ce ram 0x24) would be 80 v/ sag_thr lsb , where sag_thr lsb is the lsb value in the description of sag_thr ( table 77 ) . the parameters equ[2:0] , ce_e, and sum_samps[12:0] , essential to the function of the ce are stored in i/o ram (see 5.2 for details ). downloaded from: http:///
71m6543f/71m6543g data sheet v2 117 5.3.4 environment before starting the ce using the ce_e bit ( i/o ram 0x2106[0]) , the mpu has to establish the proper envi ronment for the ce by implementing the following steps: ? locate the ce code in flash memory using ce_lctn[5:0] ( i/o ram 0x2109[5:0] ) in the 71m6543f and ce_lctn[6 :0] ( i/o ram 0x2109[6 :0] ) in the 71m6543g . ? load the ce data into ram. ? establish the equation to be applied in equ[2:0] (i/o ram 0x2106[7:5]) . ? establis h the accumulation period and number of samples in sum_samps[12:0] (i/o ram 0x2107[4:0], 0x2108[7:0]) . ? establish the number of cycles per adc multiplexer frame ( mux_div[3:0] (i/o ram 0x2100[7:4]) ). ? apply proper values to muxn_sel , as well as proper selections for diffn_e ( i/o ram 0x210c[ ]) and rmtn_e ( i/o ram 0x2709[ ] in order to configure the analog inputs. ? initialize any mpu interrupts, such as ce_busy, xfer_busy, or the power - failure detection interrupt. when different ce codes are used, a different set of environment parameters need to be established. the exact values for these parameters are listed in the application notes and other documentation which accompanies the ce code. operating ce codes with environment parameters deviating from the values specif ied by maxim lead s to unpredictable results. typically, there are fifteen 32768 hz cycles per adc multiplexer frame (see 2.2.2 ). t his means that the product of the number of cycles per frame and the number of conversions per frame must be 14 (allowing for one settling cycle). the default configuration is fir_len = 01 , i/o ram 0x210c[1] (two cycles per conversion) and mux_div[3:0] = 7 (7 conversions per multiplexer cycle). sample configurations can be copied from demo code provided by maxim with the demo kits. 5.3.5 ce calculations referring to table 71 , the mpu selects the desired equation by writing the equ[2:0] ( i/o ram 0x2106[7:5] ). table 71 : ce equ[2:0] equations and element input mapping equ [2:0] * watt & var formula ( wsum/varsum ) w0sum/ var0sum w1sum/ var1sum w2sum/ var2sum i0sq sum i1sq sum i2sq sum 2 va*ia + vb*ib (2- element, 3 - w, 3 ? delta ) va * ia vb * ib n/a ia ib C 3 va*(ia - ib)/2 + vc*ic (2 element, 4w 3 delta) va*(ia - ib)/2 C vc*ic ia - ib ib ic 4 va*(ia - ib)/2 + vb*(ic - ib)/2 (2 element, 4w 3 wye) va*(ia - ib)/2 vb*(ic - ib)/2 C ia - ib ic - ib ic 5 va*ia + vb*ib + vc*ic (3 element, 4w 3 wye) va*ia vb*ib vc*ic ia ib ic note: * only equ[2:0] = 5 is supported by the currently available ce code versions for the 71m6 543. contact your local maxim representative for ce codes that support equations 2, 3 and 4. downloaded from: http:///
71m6543f/71m6543g data sheet 118 v2 5.3.6 ce front - end data (raw data) access to the raw data provided by the afe is possible by reading ce ram addresses 0 through a , as shown in table 72 . in the expression mux n _sel [3:0] = x, n refers to the multiplexer frame time slot number and x refers to the desired adc input number or adc handle (i. e., iadc0 to vadc10 , or simply 0 to 10 decimal). the 71m6543 can support up to eleven sensor inputs, when all the current sensors are configured as single - ended inputs. if all the current sensor inputs are configured as differential (recommended for best performance), the number of input sensor channels is reduced to seven (i.e., ia dc0 -1 , i adc2 -3 , i adc4 -5 , i adc6 -7 , va dc8 , v adc9 and v adc10 ). the mux n _sel [3:0] column in table 72 shows the mux n _sel handles for the various sensor input pins. for ex ample, if differential mode is enable d via control bit diff0 _e = 1 ( i/o ram 0x210c[4] ), then the iadc0 - iadc1 input pins are combined together to form a single differential input and the corresponding mux n _sel handle is 0 (i.e., handle 1 is then unused) . similarly, the ce ram location column provides the ce ram address where the corresponding sample data is stored. continuing with the same example, if diff0 _e = 1, the corresponding ce ram location where the samples for the iadc0 - iadc1 differential input are stored is ce ram 0. the iadc2 -3 , i adc4 -5 and i adc6 -7 input s can be configured as direct - connected sensor s (i.e., directly connected to the 71m654 3 ) or as remote sensor s (i.e., using a 71m6xx 3 isolated sensor). for example, i f the iadc2 -3 remote sensor is disabled by rmt2 _e = 0 ( i/o ram 0x2007[3] ) and differential mode is enabled by diff2 _e = 1 ( i/o ram 0x210c[4] ) , then iadc2 - iadc3 form a differential input with a mux n _sel handle of 2 (i.e., handle 3 is then unused), and the corresponding samples are stored in ce ram locati on 2. if the remote sensor enable bit rmt2 _e = 1 , diff2 _e = x (dont care) , then the mux n _sel handle is not required (i.e., the sensor is not connected to the 71m654 3 multiplexer , so mux n _sel does not apply), and the samples corresponding to this remote differential iadc2 - iadc3 input are stored in ce ram location 2 directly by the digital isolation interface (see figure 2 ). the voltage sensor inputs (va dc8 , v adc9 and v adc10 ) are always single - ended inputs and cannot be configured as remotes, so they do not have any associated configuration bits. vadc8 ( va ) has a mux n _sel handle value of 8 , and its samples are stored in ce ram location 8 . vadc9 ( vb ) has a mux n _sel han dle value of 9 and its samples are stored in ce ram location 9. vadc10 ( vc ) has a mux n _sel han dle value of 10 and its samples are stored in ce ram location 10. table 72 : ce raw data access locations pin muxn_sel handle ce ram location diff0 _e diff0 _e 0 1 0 1 iadc0 0 0 0 0 iadc1 1 1 rmt2 _e, diff2 _e rmt2 _e, diff2 _e 0,0 0,1 1,0 1,1 0,0 0,1 1,0 1,1 iadc2 2 2 - - 2 2 2* 2* iadc3 3 3 rmt4 _e, diff4 _e rmt4 _e, diff4 _e 0,0 0,1 1,0 1,1 0,0 0,1 1,0 1,1 iadc4 4 4 - - 4 4 4* 4* iadc5 5 5 rmt6 _e, diff6 _e rmt6 _e, diff6 _e 0,0 0,1 1,0 1,1 0,0 0,1 1,0 1,1 iadc6 6 6 - - 6 6 6* 6* iadc7 7 7 there are no configuration bits for vadc8 , 9, 10 vadc8 (va) 8 8 vadc9 (vb) 9 9 vadc10 (vc) 10 10 *remote interface data downloaded from: http:///
71m6543f/71m6543g data sheet v2 119 5.3.7 ce s tatus and control the ce status word is useful for generating early warnings to the mpu ( table 73 ) . it contains sag warnings for phase a, b, and c, as well as f0 , the derived clock operating at the fundamental input frequency. the mpu can read the ce status word at every ce_busy interrupt. since the ce_b usy inter rupt oc curs at the sample rate (i.e . , 2520.6 hz for mux_div[3:0] =6 or 2184.5 hz for mux_div[3:0] =7) , it is desirable to minimize the computation required in the interrupt handler of the mpu . table 73 : cestatus register ce address name description 0x80 cestatus see description of cestatus bits in table 74 . cestatus provides information about the status of voltage and input ac signal f requency, which are useful for generating an early power fail warning to initiate necessary data storage. cestatus re pre sents the status flags for the preceding ce code pass (ce_busy interrupt). the significance of the bits in cestatus is shown in table 74 . table 74 : cestatus bit definitions cestatus bit name description 31: 4 not used these unused bits are always zero. 3 f0 f0 is a square wave at the exact fundamental input frequency. 2 sag_ c normally zero. becomes one when vadc10 (vc) remains below sag_thr (ce ram 0x24) for sagcnt samples. does not return to zero until vadc10 (vc) rises above sag_thr . 1 sag_b normally zero . becomes one when vadc9 (vb) remains below sag_thr for sag_cnt samples . does not return to zero until vadc9 (vb) rises above sag_thr . 0 sag_a normally zero . becomes one when vadc8 (va) remains below sag_thr for sag_cnt samples . does not return to zero until vadc8 (va) rises above sag_thr . the ce is initialized by the mpu using ceconfig ( table 75 ). t his register contains in packed form sag_cnt, freqsel 0 , freqsel 1, ext_pulse, pulse_slow, and pulse_fast . the ceconfig bit definitions are given in table 76 . table 75 : ceconfig register ce address name data description 0x20 ceconfig 0x0030da20 see description of the ce config bits in table 76 . the ext_temp bit enables temperature compensation by the mpu, when set to 1. when 0, internal (ce) temperature compensation is enabled. the ce pulse generator can be controlled by either the mpu (external) or ce (internal) variables . control is by the mpu if ext _ pulse = 1 . in this case, the mpu controls the pulse rate by placing values into apulsew and apulser (ce ram 0x4 5 and 0x4 9) . by setting ext _ pulse = 0, the ce controls the pulse rate based on wsum_x (ce ram 0x84) and varsum_x (ce ram 0x88). the 71m6543 demo code creep function halts both internal and external pulse generation. downloaded from: http:///
71m6543f/71m6543g data sheet 120 v2 table 76 : ce config bit definitions (ce ram 0x20) ceconfig bit name default description 23 reserved 0 reserved (can be used by the mpu to indicate that the 71m6x03 is being used; ce does not use this). 22 ext_temp 0 when 1, the mpu controls temperature compensation via the gain_adjn ( ce ram 0x40 - 0x42 ) , when 0, the ce is in control. 21 ed g e_int 1 when 1, xpulse produces a pulse for each zero - crossing of the mains phase selected by freqsel[1:0] , which can be used to interrupt the mpu. 20 sag_int 1 when 1, activates the ypulse/segdio7 output when a sag is detected (see 2.5.10 ) on the phase selected with freq - sel [1 :0] . 19: 8 sag_cnt 218 (0xda ) the number of consecutive voltage samples below sag_thr ( ce ram 0x24 ) before a sag alarm is declared. the default value is equivalent to 1 0 0 ms . 7 :6 freqsel[1:0] 0 freqsel [1 :0] selects the phase to be used for the frequency monitor, sag detection, the phase - to - phase lag calculation and for the zero crossing counter ( mainedge_x , ce ram 0x83 ). fr e q sel [1:0] phase se lected phases selected ph_atob_x ph_a to c _x 0 0 a a-b a-c 0 1 b b-c b-a 1 0 c c-a c-b 1 1 not allowed 5 ext_pulse 1 when zero, causes the pulse generat o rs to respond to internal data. wpulse = wsum_x ( ce ram 0x84) , vpulse = varsum_x (ce ram 0x88.) otherwise, the generators respond to values the mpu places in apulsew and apulser (ce ram 0x4 5 and 0x4 9) 4 :2 reserved 0 reserved. 1 pulse_fast 0 when pulse_fast = 1, the pulse generator input is increased 16x . when pulse_slow = 1, the pulse generator input is re duced by a factor of 64. these two parameters control the pulse gain factor x (see table below). allowed values are e i ther 1 or 0. default is 0 for both (x = 6). pulse_ fast pulse_ slo w x 0 0 1.5 * 2 2 = 6 0 1 1.5 * 2 -4 = 0.09375 1 0 1.5 * 2 6 = 96 1 1 do not use 0 pulse_slow 0 the freqsel[1:0] field in ceconfig ( ce ram 0x20[7:6] ) selects the ph ase that is utilized to generate a sag interrupt . thus, a sag_int event occurs when the selected phase has satisfied the sag event criteria as set by the sag_thr ( ce ram 0x24 ) register and the sag_cnt field in ceconfig (ce ram 0x20[19:8]). when the sag_int bit ( ce ram 0x20[20] ) is set to 1, a sag event generates a transition on the ypulse output. after a sag interrupt, the mpu should change the freqsel[1:0] setting to select the other phase, if it is powered. even though a sag interrupt is only generated on the sel ected phase, all three phases are simultaneously checked for sag. the presence of power on a given phase can be sens ed by directly checking the sag_a , sag_b and sag_c bits in cestatus ( ce ram 0x80[0:1]). the ext_temp bit enables temperature compensation by the mpu, when set to 1. when 0, internal (ce) temperature compensation is enabled. downloaded from: http:///
71m6543f/71m6543g data sheet v2 121 the ce pulse generator can be controlled by either the mpu (exter nal) or ce (internal) variables. control is by the mpu if the ext _ pulse bit = 1 ( ce ram 0x20[5] ) . in this case, the mpu controls the pulse rate (external pulse generation) by placing values into apulsew and apulser (ce ram 0x4 5 and 0x4 9) . by setting ext _ pulse = 0, the ce controls the pulse rate based on wsum_x (ce ram 0x84) and varsum_x (ce ram 0x88). the 71m6543 demo code creep function halts both internal and external pulse generation. table 77 : sag threshold , phase measurement, and gain adjust control ce address name default description 0x24 sag_thr 2.39*10 7 the voltage threshold for sag warnings. the default value is equivalent to 80vrms if vmax = 600v. sag_thr = ? ??? ? 2 ???? ?7 . 8798 ? 10 ?9 0x40 gain_adj0 16384 the assignments of these gain adjustments depends on the meter design. see 4.5.4 temperature compensation for vref and shunt sensors on page 89 or 4.5.5 temperature compensation of vref and current transformers on page 90 . the default value of 16384 corresponds to unity gain. 0x41 gain_adj1 16384 0x42 gain_adj2 16384 0x43 gain_adj3 16384 0x44 gain_adj4 16384 5.3.8 ce transfer v ariables when the mpu receives the xfer_busy interrupt, it knows that fresh dat a is available in the transfer variables . ce trans fer variables are modified during the ce code pass that ends with an xfer_bu sy interrupt. they remain constant throughout each accumulation interval. in this data sheet, the names of ce transfer variables always end with _x. the transfer variables can be categorized as: ? fundamental energy measurement variables ? instantaneous (rms) values ? other measurement parameters fundamental energy measurement variables table 78 describes each transfer variable for fundamental energy measurement . all variables are signed 32 - bit integers . accumulated variables such as wsum are internally scaled so they have at leas t 2x margin before overflow when the integration time is one second . additionally, the hardware does not permit output values to fold back upon overflow . table 78 : ce transfer variables (with shunts) ce address name description configuration 0x84 wsum_x the signed sum: w0sum_x+w1sum_x+w2sum_x . figure 31 (page 86 ) 0x85 w0sum_x the sum of wh samples from each wattmeter element . lsb w = 7.7562 *10 -13 vmax * imax wh. 0x86 w1sum_x 0x87 w2sum_x 0x88 varsum_x the signed sum: var0sum_x+var1sum_x+var2sum_x . 0x89 var0sum_x the sum of var h samples from each wattmeter element . lsb w = 7.7562 *10 -13 vmax * imax var h. 0x8a var1sum_x 0x8b var2sum_x downloaded from: http:///
71m6543f/71m6543g data sheet 122 v2 table 79 : ce transfer variables (with cts) ce address name description configuration 0x84 wsum_x the signed sum: w0sum_x+w1sum_x+w2sum_x . figure 32 (page 87 ) 0x85 w0sum_x the sum of wh samples from each wattmeter element . lsb w = 1.0856 *10 -12 vmax imax wh. 0x86 w1sum_x 0x87 w2sum_x 0x88 varsum_x the signed sum: var0sum_x+var1sum_x+var2sum_x . 0x89 var0sum_x the sum of var h samples from each wattmeter element . lsb w = 1.0856 *10 -12 vmax imax var h. 0x8a var1sum_x 0x8b var2sum_x w sum_x and varsum_x are the signed sum of phase - a, phase - b and phase - c wh or varh values ac cording to the metering equation specified in the control field equ[2:0] (i/o ram 0x2106[7:5]) . wn sum_x is the wh value accumulated for phase n in the last accumulation interval and can be computed based on the specified lsb value. for example , with vmax = 600 v and imax = 208 a, the lsb for wn sum_x is 0. 135 wh. 5.3.8.1 instantaneous energy measurement variables in sqsum_x and vn sqsum are the squared current and voltage samples acquired during the last acc umulation interval. insqsum_x can be used for computing the neutral current. table 80 : ce energy measurement variables (with shunts) ce address name description configuration 0x8c i0sqsum_x neutral current: lsb i = 9.9045*10 - 13 * imax 2 a 2 h ( pre_e =0) lsb i = 6.1903125*10 - 14 * imax 2 a 2 h ( pre_e =1) figure 31 (page 86 ) 0x8d i1sqsum_x lsb i = 6.3968*10 - 13 * (imax 2 ) a 2 h 0x8e i2sqsum_x 0x8f i3sqsum_x 0x90 v0sqsum_x lsb v = 9.4045*10 - 13 *vmax 2 v 2 h 0x91 v1sqsum_x 0x92 v2sqsum_x table 81 : ce energy measurement variables (with cts) ce address name description configuration 0x8c i0sqsum_x lsb i = 1.0856 *10 -12 * ( imax 2 ) a 2 h figure 32 (page 87 ) 0x8d i1sqsum_x 0x8e i2sqsum_x 0x8f i3sqsum_x 0x90 v0sqsum_x lsb v = 1.0856 *10 -12 * vmax 2 v 2 h 0x91 v1sqsum_x 0x92 v2sqsum_x downloaded from: http:///
71m6543f/71m6543g data sheet v2 123 the rms values can be computed by the mpu from the squared current and voltage samples as follows: other transfer variables include those available for frequency and phase m easurement, and those re flecting the count of the zero - crossings of the mains voltage and the battery voltage. these transfer variables are listed in table 82 . mainedge_x reflects the number of half - cycles accounted for in the last accumulated interval for the ac signal of the phase specified in the freqsel [1 :0] field of the ceconfig register ( ce ram 0x20[7:6] ) . mainedge_x is useful for implementing a real - time clock based on the input ac signal. table 82 : other transfer variables ce address name description 0x82 freq_x fundamental frequency : lsb 6 32 10 509 .0 2 2184 ? ? hz hz (for ct) lsb 6 32 10 587 .0 2 2520 ? ? hz hz (for shunt) 0x83 mainedge_x the number of edge crossings of the selected voltage in the pre vious ac cumulation interval. edge crossings are either direction and are debounced. 0x94 ph_atob_x voltage phase lag. the selection of the reference phase is based on freqsel [1: 0] in the c ec onfig register: if freqsel [1 :0] se lect s phase a: phase lag from a to b. if freqsel [1 :0] select s phase b: phase lag from b to c. if freqsel [1 :0] select s phase c: phase lag from c to a. a ngle in degrees is (0 to 360): ph_atob_x * 360/n acc + 2.4 *15/13 (for ct) a ngle in degrees is (0 to 360): ph_atob_x * 360/n acc + 2.4 (for shunt) 0x95 ph_atoc_x if freqsel [1 :0] select s phase a: phase lag from a to c. if freqsel [1 :0] select s phase b: phase lag from b to a. if freqsel [1 :0] select s phase c: phase lag from c to b. angle in degrees is (0 to 360): ph_atoc _x * 360/n acc + 4.8*15/13 (for ct) angle in degrees is (0 to 360): ph_atoc _x * 360/n acc + 4.8*15/13 (for shunt) phase angle measurement accuracy can be increased by writing values > 1 into v_ang_cnt ( v_ang_cnt indicates how many accumulation periods to sum ph_atob_x and ph_atoc_x over. the mpu then has to divide by that number. for standard ce codes that s upport shunts with remotes, v_ang_cnt is at ce address 0x53. for standard ce codes that support shunts with ct, v_ang_cnt is at ce address 0x55. for other than standard ce codes, please contact maxim for information). 5.3.9 pulse generation table 83 describes the ce pulse generation parameters . the combination of the ceconfig pulse_slow (ce ram 0x20[0] ) and pulse_fast (ce ram 0x20[1] ) bits control s the speed of the pulse rate. the default values of 0 and 0 maintain the original pulse rate given by the kh equation. wrate ( ce ram 0x21 ) controls the number of pulses that are generated per measured wh and varh quantities. the lower wrate is the slower the pulse rate for measured energy quantity. the metering con stant kh is derived from wrate as the amount of energy measured for each pulse. that is, if kh = acc s i rms n f lsb ixsqsum ix ? ? ? = 3600 acc s v rms n f lsb vxsqsum vx ? ? ? = 3600 downloaded from: http:///
71m6543f/71m6543g data sheet 124 v2 1wh/pulse, a power applied to the meter of 120 v and 30 a results in one pulse per second. if the load is 240 v at 150 a, ten pulses per second are generated. control is transferred to the mpu for pulse generation if ext_pulse = 1 (ce ram 0x20[5]) . in this case, the pulse rate is de termined by apulsew and a pulser (ce ram 0x4 5 and 0x4 9) . the mpu has to load the source for pulse generation in apulsew and apulser to generate pulses. irrespective of the ext_pulse status , the output pulse rate controlled by apulsew and apulser is implemented by the ce only. by setting ext_pulse = 1 , the mpu is providing the source for pulse generation. if ext_pulse is 0 , w0sum_x and var0sum_x are the default pulse generation sources. in this case, creep cannot be con trolled since it is an mpu function. the maximum pulse rate is 3*f s = 7.5 khz . see 2.3.6.2 vpulse and wpulse (page 27 ) for details on how to adjust the timing of the output pulses. the maximum time jitter is 1/6 of the multiplexer cycle period (nominally 67 s) and is independent of the number of pulses measured. thus, if the pulse generator is monitored for one second, the peak jitter is 67 ppm. after 10 seconds, the peak jitter is 6.7 ppm. the average jitter is always zero. if it is attempted to drive either pulse generator faster than its maximum rate, it sim ply output s at its maximum rate without exhibiting any rollover characteristics. the actual pulse rate, using wsum as an example, is: hz x f wsum wrate rate s 46 2 ? ? ? = , where f s = sampling frequency (2184 . 53 hz), x = pulse speed factor derived from the ce variables pulse_slow (ce ram 0x20[0]) and pulse_fast (ce ram 0x20[ 1 ]) . downloaded from: http:///
71m6543f/71m6543g data sheet v2 125 table 83 : ce pulse generation parameters ce address name default description 0x21 wrate 22 7 kh = vmax*imax* k / ( wrate *n acc *x) wh/pulse where: k = 76.3594 when used with local sensors (ct or shunt) k = 54.5793 when used with 71m6xx3 remote sensors 0x22 kvar 644 4 scale factor for var measurement. 0x23 sum_pre 2184 number of samples per accumulation interval, as specified in sum_samps[12:0] , i/o ram 0x2107[4:0], 0x2108[7:0] (n acc ). 0x4 5 apulsew 0 wh pulse (wpulse) generator input to be updated by the mpu when using external pulse generation . the output pulse rate is: apulsew * f s * 2 - 32 * wrate * x * 2 - 14 . thi s input is buffered and can be updated by the mpu during a conversion interval. the change take s effect at the beginning of the next interval. 0x4 6 wpulse_ctr 0 counter for wpulse output. 0x4 7 wpulse_ frac 0 unsigned numerator, containing a fraction of a pulse. the value in this register always count s up towards the next pulse. 0x4 8 wsum_ accum 0 roll - over accumulator for wpulse. 0x4 9 apulser 0 var h ( vpulse ) pulse generator input . 0x4 a vpulse _ctr 0 counter for vpulse output. 0x4 b vpulse _ frac 0 unsigned numerator, containing a fraction of a pulse. the value in this register always count s up towards the next pulse. 0x4 c vsum_accum 0 roll - over accumulator for vpulse . other ce parameters table 84 shows the quant ce parameters used for suppression of noise due to scaling and truncation effects. the equations for calculating the lsb weight of each quant parameter are provided at the bottom of table 84 . downloaded from: http:///
71m6543f/71m6543g data sheet 126 v2 table 84 : ce parameters for noise suppression and code versio n ce address name default description 0x2 6 quant _ia 0 compensation factors for truncation and noise in current, real energy and reactive energy for phase a. 0x27 quant_wa 0 0x28 quant_ vara 0 0x2 a quant _ib 0 compensation factors for truncation and noise in current, real energy and reactive energy for phase b. 0x2b quant_wb 0 0x2c quant_varb 0 0x2 e quant _ic 0 compensation factors for truncation and noise in current, real energy and reactive energy for phase c. 0x2f quant_wc 0 0x30 quant_varc 0 0x31 quant_id 0 compensation factors for truncation and noise in current for phase d. lsb weights for use with the 71m6xx3 isolated sensors : ) ( 10 20864 .5 _ _ 2 2 10 amps imax lsb ix quant ? ? = ? ) ( 10 59147 .8 _ _ 10 watts imax vmax lsb wx quant ? ? ? = ? ) ( 10 59147 .8 _ _ 10 vars imax vmax lsb varx quant ? ? ? = ? lsb weights for use with current transformers (cts): ) ( 10 08656 .5 _ _ 2 2 13 amps imax lsb ix quant ? ? = ? ) ( 10 04173 .1 _ _ 9 watts imax vmax lsb wx quant ? ? ? = ? ) ( 10 04173 .1 _ _ 9 vars imax vmax lsb varx quant ? ? ? = ? downloaded from: http:///
71m6543f/71m6543g data sheet v2 127 5.3.10 ce calibration parameters table 85 lists the parameters that are typically entered to effect calibration of meter accuracy. table 85 : ce calibration parameters ce address name default description 0x10 cal_ia 16384 these constants control the gain of their respective channels. the n ominal value for each parameter is 2 14 = 16384. the gain of each channel is directly proportional to its cal parameter. thus, if the gain of a channel is 1% low, cal shou ld be increased by 1%. 0x11 cal_va 16384 0x13 cal_ib 16384 0x14 cal_vb 16384 0x16 cal_ic 16384 0x17 cal_vc 16384 0x19 cal_i d 16384 0x1 2 phadj_a 0 these constants control the ct phase compensation. no com pensation occurs when phadj_x = 0. as phadj_x is increased, more compensation (lag) is introduced. the r ange is 2 15 C 1. if it is desired to delay the current by the angle , the equations are : ? ? = tan tan x phadj 0168 .0 1714 .0 029615 .0 2 _ 20 at 60hz ? ? ? = tan tan x phadj 01226 .0 1430 .0 0206 .0 2 _ 20 at 50hz 0x1 5 phadj_b 0 0x1 8 phadj_c 0 0x12 dlyadj_a 0 the shunt delay compensation is obtained using the equation provided below: ( ) ? ?? ? ? ?? ? + ? ?? ? ? ?? ? + ? ?? ? ? ?? ? ? + ?= s s s rees rees f f c b f f ab f f a x dlyadj 2 sin 2 cos 2 2 cos 360 2 2 1.0 1 _ 2 2 14 deg deg where: a a 2 = 1 2 + = a b ? = 2 ? 2 + 4 ???? ? 2 ?? ? ? ? + 2 f is the mains frequency f s is the sampling frequency the table below provides the value of a for each channel: channel value of a (decimal) d yadj_a 13840 dlyadj_ b 11693 dlyadj_ c 9359 0x15 dlyadj_b 0 0x18 dlyadj_c 0 note: the current sensor inputs are not assigned to the a, b and c phases in a fixed m anner. the assignments of phases a, b and c depends on how the iadc0 - 1, iadc2 - 3, iadc4 - 5, iadc6 - 7 current sensing inputs are connected in the meter design. the ce code must be aware of these connections. see figure 31 and figure 32 for typical meter configurations. vadc8, vadc9 and vadc10 are assigned to voltage phases va, vb and vc in a fixed manner, respectively. the ce addresses listed in this table are assigned to phases a, b and c as ind icated by their names. downloaded from: http:///
71m6543f/71m6543g data sheet 128 v2 5.3.11 ce flow diagrams figure 38 through figure 40 show the data flow through the ce in simplified form. functions not shown include delay compensation, sample interpolation, scaling and the processing of m eter equations. figure 38 : ce data flow: multiplexer and adc figure 39 : ce data flow: scaling, gain control, intermediate varia bles for one phase vref multiplexer f s = 2184 hz ? mod deci - mator de - multiplexer f s = 2184 hz ia_raw ia vb va ib ic vc ib_raw va_raw vb_raw ic_raw vc_raw i d i d _raw downloaded from: http:///
71m6543f/71m6543g data sheet v2 129 figure 40 : ce data flow: squaring and summation stages v ia wa square wb vara varb va iasq vasq ibsq sum iasqsum_x vasqsum_x icsqsum_x sum wasum_x wbsum_x varasum_x varbsum_x sum_samps = 2184 mpu f0 i 2 v 2 wc varc wcsum_x varcsum_x ibic vb vc icsq vbsq vcsq ibsqsum_x vbsqsum_x vcsqsum_x f0 id idsq idsqsum_x downloaded from: http:///
71m6543f/71m6543g data sheet 130 v2 6 71m6543 specifications this section provides the electrical specifications for the 71m6543. pleas e refer to the 71m6xxx data sheet for the 71m6xx3 electrical specifications, pin - out and package mechanical data. 6.1 a bsolute m aximum r atings table 86 shows the abs olu te maximum ratings for the device. stresses beyond absolute maximum ratings may ca use permanent damage to the device. these are stress ratings only and functional operation at these or any other conditions beyond those indicated under recommended operating condit ions ( see 6.3 ) is not implied. exposure to absolute - maximum - rated conditions for extended periods may affect device reliability. all voltages are with respect to gnda. table 86 : absolute maximum ratings voltage and current supplies and ground pins v3p3sys, v3p3a ? 0.5 v to + 4.6 v vbat , vbat_rtc - 0.5 v to + 4.6 v gndd - 0.1 v to +0.1 v analog output pins vref - 10 ma to +10 ma, - 0.5 v to v3p3a+0.5 v vdd - 10 ma to + 10 ma, - 0.5 to + 3.0 v v3p3d - 10 ma to +10 ma, - 0.5 v to 4.6 v vlcd - 10 ma to + 10 ma, - 0.5 v to + 6 v analog input pins i adc0 , i adc1 , i adc2 , i adc3 , i adc4 , i adc5 , i adc6 , i adc7, vadc8 , v adc9 and v adc10 - 10 ma to +10 ma - 0.5 v to v3p3a+0.5 v xin, xout - 10 ma to +10 ma - 0.5 v to + 3.0 v seg and segdio pins configured as seg or com drivers - 1 ma to + 1 ma, - 0.5 v to vlcd+0.5 v configured as digital inputs - 10 ma to + 10 ma, - 0.5 v to + 6 v configured as digital outputs - 10 ma to + 10 ma, - 0.5 v to v3p3d+0.5 v digital pins inputs (pb, reset, rx, ice_e, test) - 10 ma to + 10 ma, - 0.5 to 6 v outputs (tx) - 10 ma to + 10 ma, - 0.5 v to v3p3d+0.5 v temperature operating junction temperature (peak, 100ms) 140 c operating junction temperature (continuous) 125 c storage temperature ? 45 c to +165 c soldering t emperature C 10 second duration 250 c downloaded from: http:///
71m6543f/71m6543g data sheet v2 131 6.2 recommended external components table 87 : recommended external components name from to function value unit c1 v3p3a gnda bypass capacitor for 3.3 v supply 0.1 20% f c2 v3p3d gndd bypass capacitor for 3.3 v output 0.1 20% f csys v3p3sys gndd bypass capacitor for v3p3sys 1.0 30% f cvdd vdd gndd bypass capacitor for v dd 0.1 20% f cv lc d vlc d gndd bypass capacitor for v lc d pin 0.1 20% f xtal xin xout 32.768 khz crystal C electrically equivalent to ecs .327 - 12.5 - 17x or vishay xt26t, load capacitance 12.5 pf 32.768 khz cxs xin gnda load capacitor values for crystal de pend on crystal spec ification s and board parasit ics . nominal values are based on 4 pf board capacitance and include an allowance for chip capacitance. 15 10% pf cxl xout gnda 10 10% pf 6.3 r ecommended operating c onditions unless otherwise specified, a ll parameters listed under 6.4 performance sp ecifications and 6.5 timing specifications are valid over the recommended operating conditions provided in table 88 below. table 88 : recommended operating conditions p arameter condition min typ max unit v3p3sys and v3p3a supply voltage for precision metering operation (msn mode) . voltages at vbat and vbat_rtc need not be present. vbat=0 v to 3.8 v vbat_rtc =0 v to 3.8 v 3.0 3.6 v vbat voltage (brn mode). v3p3sys is below the 2.8 v comparator threshold. either v3p3sys or vbat_rtc must be high enough to power the rtc module. v3p3sys < 2.8 v and max(vbat_rtc, v3p3sys) > 2.0 v 2.5 3.8 v vbat_rtc voltage. vbat_rtc is not needed to support the rtc and non - volatile memory unless v3p3sys<2.0 v v3p3sys<2.0 v 2.0 3.8 v operating temperature - 40 +85 oc notes: 1. gnda and gndd must be connected together. 2. v3p3sys and v3p3a m u st be connected together. downloaded from: http:///
71m6543f/71m6543g data sheet 132 v2 6.4 p erformance s pecifications 6.4.1 input logic levels table 89 : i nput logic levels p arameter c ondition m in t yp m ax u nit digital high - level input voltage 1 , v ih 2 v digital low - level input voltage 1 , v il 0.8 v input pullup current, i il e_rxtx, e_ rst , e_tclk opt_rx, opt_tx spi_csz (segdio36) other digital inputs vin=0 v , ice_e= 3.3 v 10 10 10 -1 0 100 100 10 0 1 a a a a input pull down current, i ih ice_e, reset, test other digital inputs vin=v3p3d 10 -1 0 100 1 a a note: 1. in battery powered modes, di gital inputs should be below 0.1 v or above v bat C 0.1 v to minimize battery current. 6.4.2 o utput logic levels table 90 : output logic levels p arameter c ondition m in t yp m ax u nit digital high - level output voltage v oh i load = 1 ma v3p3d C 0.4 v i load = 15 ma (see notes 1, 2) v3p3d - 0.6 v digital low - level output voltage v ol i load = 1 ma 0 0.4 v i load = 15 ma (see note 1) 0 0.8 v note: 1. guaranteed by design; not production tested. 2. caution: the sum of all pull up currents must be compatible with the on - resistance of the internal v3p3d switch . s ee 6.4.6 v3p3d switch on page 136 . downloaded from: http:///
71m6543f/71m6543g data sheet v2 133 6.4.3 battery monitor table 91 : batter y monitor performance specifications ( temp_bat = 1) parameter condition min typ max unit bv: battery voltage (definition) msn mode, temp_pwr = 1 brn mode, temp_pwr = temp_bsel ?? = 3.3 ? + ( ?????? ? 142 ) ? 0. 0246 ? + ????? ? 297 ?? ?? = 3. 291 ? + ( ?????? ? 142 ) ? 0. 0255 ? + ????? ? 328 ?? v measurement error ?? ? ?? ? ? ? 1 100 vbat bv vbat = 2.0 v 2.5 v 3 .0 v 4.0 v - 7.5 -5 -3 -3 7.5 5 3 5 % % % % input impedance in continuous measurement, msn mode. v (vbat_rtc)/i(vbat_rtc) v3p3 = 3.3 v, temp_bsel = 0, temp_per = 111, vbat_rtc = 3.6 v, 1 m? load applied with bcurr ibat( bcurr =1) - ibat( bcurr =0) v3p3 = 3.3 v 50 100 140 a downloaded from: http:///
71m6543f/71m6543g data sheet 134 v2 6.4.4 temperature monitor table 92 : temperature monitor parameter condition min typ max unit temperature measurement equation for 71m6543f and 71m6543g (see note s 2 and 3) in msn, temp_pwr =1: ???? = 0. 325 ? ????? + 22 in brn, temp_pwr = temp_bsel : ???? = 0. 325 ? ????? + 0. 00218 ? ?????? 2 ? 0. 609 ? ?????? + 64 .4 c temperature error (71m6543) (see note 1) t a = 22 ? c -2 2 c vbat_rtc charge per measurement temp_ bsel = 0, temp_p wr =0, slp mode, vbat_rtc = 3.6 v 16 c duration of temperature measurement after setting temp_start (see note 1) 15 60 ms note s: 1. guaranteed by design; not production tested. 2. for the 71m6543f and 71m6543g, temp_85 fuses read 0. 3. the coefficients provided in these equations are typical. downloaded from: http:///
71m6543f/71m6543g data sheet v2 135 6.4.5 s upply c urrent the supply currents provided in table 93 below include only the current consumed by the 71m6543. refer to the 71m6xxx data sheet for additional current required when using a 71m6x03 remote sensor. table 93 : supply current performance specifications parameter condition device min typ max unit i1: v3p3a + v3p3sys current, normal operation polyphase : 4 currents, 3 voltages v3p3a = v3p3sys = 3.3 v, mpu_div [2:0] = 3 (614 khz mpu clock), no flash memory write, rtm_e =0, pre_e =0, ce_e =1, adc_e =1, adc_div =0, mux_div[3:0] =7, fir_len[1:0] =1, pll_fast =1 71m6543f 7.2 8.5 ma 71m6543g 7.5 8.8 i1a: v3p3a + v3p3sys current, adc half rate ( adc_div=1 ) same as i1, except adc_div =1, fir_len =0 71m6543f 6.4 7.3 ma 71m6543g 6.7 7.7 i1b: v3p3a + v3p3sys current, normal operation pll_fast =0 same as i1, except pll_fast =0 71m6543f 2.9 3.8 ma 71m6543g 3.0 3.9 i1c: v3p3a + v3p3sys current, normal operation pre_e =1 same as i1, except pre_e =1 71m6543f 7.3 8.7 ma 71m6543g 7.7 9.1 i1d: v3p3a + v3p3sys current, normal operation pre_e =1, adc_div =1, fir_len =0. (see note 1) same as i1, except pre_e =1, adc_div =1, fir_len =0. 71m6543f 6.5 7.5 ma 71m6543g 6.9 7.9 i1e: v3p3a + v3p3sys current, normal operation pll_fast =0, pre_e =1. (see note 1) same as i1, except pre_e =1, pll_fast =0. 71m6543f 3.0 3.9 ma 71m6543g 3.1 3.9 i2: v3p3a + v3p3sys dynamic current same as i1, except with varia tion of mpu_div[2:0] . 4.3 i- i 3 mpu_div 0 mpu_div = = 71m6543f 0.4 0.6 ma/ mhz 71m6543g 0.5 0.65 vbat current i3: msn mode i4: brn mode i5: lcd mode (ext. vlcd) i6: lcd mode (boost, dac) i7: lcd mode (dac) i8: lcd mode (vbat) i9: slp mode ce_e =0 lcd_vmode[1:0] =3, also see note 3 lcd_vmode[1:0] =2, also see notes 1, 2 lcd_vmode[1:0] =1, also see notes 1, 2 lcd_vmode[1:0] =0, also see notes 1, 2 slp mode 71m6543 71m6543f 71m6543g 71m6543 71m6543 71m6543 71m6543 71m6543 - 300 - 300 0 2.4 2.6 0.4 24 3.0 1.1 0 300 3.2 3.5 108 36 11 3.4 +300 na ma ma na a a a na vbat_rtc current i10: msn i11: brn i12: lcd mode i13: slp mode i14: slp mode (see note 1) lcd_vmode[1:0] =2, also see note 3 t a 25 c t a = 85 c 71m6543 71m6543f /g 71m6543g 71m6543 71m6543 71m6543 - 300 0 240 260 1.8 0.7 1.5 300 410 420 4.1 1.7 3.2 na na na a a a i15: v3p3a + v3p3sys current, write flash with ice same as i1, except write flash at maximum rate, ce_e =0, adc_e =0. 71m6543f/g 7.1 8.7 ma 71m6543g 7.3 8.7 notes: 1. guaranteed by design; not production tested. 2. lcd_dac[4:0] =5 (2.9v), lcd_clk[1:0] =2, lcd_mode[2:0] =6, all lcd_mapn bits = 0. 3. lcd_dac[4:0] =5 (2.9v), lcd_clk[1:0] =2, lcd_mode[2:0] =6, lcd_blank =0, lcd_on =1, all lcd_mapn bits = 1 and vlcd pin = 3.3v. downloaded from: http:///
71m6543f/71m6543g data sheet 136 v2 6.4.6 v3p3d s witch table 94 : v3p3d switch performance specifications p arameter c ondition m in t yp max unit on resistance C v3p3sys to v3p3d | i v3p3d | 1 ma 10 on resistance C vbat to v3p3d | i v3p3d | 1 ma , vbat>2.5v 10 v3p3d i oh , msn v3p3sys = 3v v3p3d = 2.9v 10 ma v3p3d i oh , brn vbat = 2.6v v3p3d = 2.5v 10 ma 6.4.7 internal power fault comparators table 95 : internal power fault comparators performance specifications p arameter condition m in t yp max unit overall response time 100mv overdrive, falling 100mv overdrive, rising 20 200 200 s s falling threshold 3.0 v comparator 2.8 v comparator difference 3.0v and 2.8v comparators v3p3 falling 2.8 3 2.75 50 2.93 2.81 136 3.03 2.87 220 v v mv falling threshold 2.25 v comparator 2.0 v comparator vdd (@vbat=3.0v) C 2.25v comparator difference 2.25v and 2.0v comparators vdd falling 2. 2 1.9 0 0.25 0.15 2.25 2.00 0.35 0.25 2.5 2. 20 0.45 0.35 v v v v hysteresis, (r ising threshold - f alling thre shold ) 3.0 v comparator 2.8 v comparator 2.25 v comparator 2.0 v comparator t a = 22 c 22 25 10 10 45 42 33 28 65 60 60 60 mv mv mv mv 6.4.8 2.5 v v oltage r egulator C system power table 96 : 2.5 v voltage regulator performance specifications p arameter c ondition m in t yp max unit v2p5 v3p3 = 3.0 v - 3.8 v i load = 0 ma 2.55 2. 65 2.7 5 v v2p5 load regulation v3p3 = 3.3 v i load = 0 ma to 5 ma 40 mv voltage overhead v3p3 sys - v2p5 i load = 5 ma, reduce v3p3d until v2p5 drops 200 mv 440 mv downloaded from: http:///
71m6543f/71m6543g data sheet v2 137 6.4.9 2.5 v v oltage r egulator C battery power table 97 : low - power voltage regulator performance specifications p arameter c ondition m in t yp max unit v2p5 vbat = 3.0 v - 3.8 v, v3p3 = 0 v, i load = 0 ma 2.55 2. 65 2.7 5 v v2p5 load regulation vbat = 3.3 v, v3p3 = 0 v, i load = 0 ma to 1 ma 40 mv voltage overhead 2v ? vbat - vdd i load = 0 ma, vbat = 2.0 v , v3p3 = 0 v. 20 0 mv 6.4.10 c rystal o scillator table 98 : crystal oscillator performance specifications p arameter c ondition m in t yp max unit maximum output power to crystal crystal connected, see note 1 1 w xin to xout capacitance (see note 1) 3 pf capacitance change on xout rtc a _adj = 7f to 0, bias voltage = unbiased vpp = 0.1 v 15 pf note: 1. guaranteed by design; not production tested. 6.4.11 phase - locked loop ( pll ) table 99 : pll performance specifications parameter condition min typ max unit pll power - up settling time pll_fast =0, v3p3 = 0 to 3.3 v step measured from first edge of mck (tmux2out pin) 3 ms pll_fast settling time pll_fast rise pll_fast fall v3p3=0, vbat=3.8 to 2.0 v 3 3 ms ms pll slp to msn settling time pll_fast =0 3 ms 6.4.12 lcd d rivers table 100 : lcd drivers performance specifications parameter condition min typ max unit vlcd current vlcd=3.3, all lcd map bits=0 vlcd=5.0, all lcd map bits=0 2 3 ua ua note: 1. these specifications apply to all com and seg pins. 1. lcd_vmode =3, lcd_on =1, lcd_blank =0, lcd_mode =6, lcd_clk =2. 2. output load is 74 pf per seg and com pin. downloaded from: http:///
71m6543f/71m6543g data sheet 138 v2 6.4.13 vlcd generator table 101 : vlcd generator specifications parameter condition min typ max unit vsys to vlcd switch impeda nce v3p3 = 3.3 v , rvlcd=removed, lcd_bat =0, lcd_vmode [1:0] =0, ?ilcd=10 a 75 0 ? vbat to vlcd switch impeda nce v3p3 = 0 v , vbat = 2.5 v, rvlcd =removed, lcd_bat =1, lcd_vmode [1:0] =0, ?ilcd=10 a 700 ? lcd boost frequenc y lcd_vmode [1:0] = 2 , rvlcd = removed, cvlcd = removed pll_fast =1 pll_fast =0 820 786 khz khz vlcd ioh current (vlcd(0)- vlcd(ioh)<0.25) lcd_vmode [1:0] = 2 , lcd_clk[1:0] = 2, rvlcd = removed, v3p3 = 3.3 v, lcd_dac [4:0] = 1f 10 a from lcdadj0 and lcdadj12 fuses: ?????? ( ??? _ ??? ) = 5 ?? ? ?????? 0 + ?????? 12 ? ?????? 0 12 ??? _ ??? ? ???? ??? ( ??? _ ??? ) = 2. 65 + 2. 65 ??? _ ??? 31 + ?????? ( ??? _ ??? ) the above equations describe the nominal value of vlcd for a specific lcd_dac value. the specifications below list the maximum deviation between actual vlcd a nd vlcdnom. note that when vcc and boost are insufficient, the lcd dac will not reach its target val ue and a large negative error will occur. lcd _dac error. vlcd - vlcdnom full scale, with boost v3p3 =3.6 v v3p3 =3.0 v vbat=4.0 v , v3p3=0, brn mode vbat=2.5 v , v3p3=0, brn mode lcd_vmode = 10 , lcd_dac [4:0] = 1f , lcd_clk[1:0] =2, lcd_mode[2:0] =6 - 0.15 - 0. 4 - 0.15 -1 .3 0.15 0.15 0.15 v v v v lcd_dac error. vlcd - vlcdnom dac=12 , with boost v3p3 = 3.6 v v3p3 = 3.0 v vbat = 2.5 v , v3p3 = 0 v , brn mode lcd_vmode = 10 , lcd_dac [4:0] = c, lcd_clk[1:0] =2, lcd_mode[2:0] =6 - 0.15 - 0.15 - 0.15 0.15 0.15 0.15 v v v lcd_dac error. vlcd - vlcdnom zero scale, with boost v3p3 = 3.6 v v3p3 = 3.0 v vbat = 4.0 v , v3p3 = 0 v , brn mode vbat = 2.5 v , v3p3 = 0 v , brn mode lcd_vmode = 2, lcd_dac [4:0] =0 , lcd_clk[1:0] =2, lcd_mode[2:0] =6 - 0.15 - 0.15 - 0.15 - 0.15 0.15 0.15 0.15 0.15 v v v v lcd_dac error. vlcd - vlcdnom full scale, no boost v3p3 = 3.6 v (see note 1) v3p3 = 3.0 v (see note 1) vbat = 4.0 v , v3p3 = 0 v , brn mode vbat = 2.5 v , v3p3 = 0 v , brn mode lcd_vmode = 1, lcd_dac [4:0] = 1f , lcd_clk[1:0] =2, lcd_mode[2:0] =6 - 2.1 - 2.8 - 1.8 - 3.2 v v v v lcd_dac error. vlcd - vlcdnom dac=12 , no boost v3p3 = 3.6 v v3p3 = 3.0 v vbat = 4.0 v , v3p3 = 0 v , brn mode vbat = 2.5 v , v3p3 = 0 v , brn mode lcd_vmode = 1, lcd_dac [4:0] = c, lcd_clk[1:0] =2, lcd_mode[2:0] =6 -0 .5 - 1.1 - 0.15 1 - 1.5 1 0.15 1 v v v v downloaded from: http:///
71m6543f/71m6543g data sheet v2 139 parameter condition min typ max unit lcd_dac error. vlcd - vlcdnom zero scale, no boost v3p3 = 3.6 v v3p3 = 3.0 v vbat = 4.0 v , v3p3 = 0 v , brn mode vbat = 2.5 v , v3p3 = 0 v , brn mode lcd_vmode = 01 , lcd_dac [4:0] = 0, lcd_clk[1:0] =2, lcd_mode[2:0] =6 - 0.15 - 0.15 - 0.15 - 0.45 0.15 0.15 0.15 0.15 v v v v lcd_dac error. vlcd - vlcdnom full scale, with boost, lcd mode vbat = 4.0 v , v3p3 = 0 v vbat = 2.5 v , v3p3 = 0 v lcd_vmode = 1, lcd_dac [4:0] = 1f , lcd_clk[1:0] =2, lcd_mode[2:0] =6 - 0.15 -1 .3 0.15 v v note: 1. guaranteed by design; not production tested. 2. the following test condition s also apply to all parameters provided in this table: b ypass capacitor cvlcd 0.1 f, test load rvlcd = 500 k , no display, all segdio pins configured as dio. downloaded from: http:///
71m6543f/71m6543g data sheet 140 v2 6.4.14 71m6543 vref table 102 shows the performance specifications for the 71m6543 adc reference voltage ( vref ) . table 102 : 71m6543 vref performance specifications p arameter c ondition m in t yp max unit vref output voltage, vref(22 ) t a = 22 oc 1.193 1.195 1.197 v vref output voltage, vref(22 ) pll_fast =0 1.195 v vref chop step , trimmed vref(chop=01) ? vref(chop=10) - 10 10 mv vref power supply sensitivity vref / v3p3a v3p3a = 3.0 to 3.6 v - 1.5 1.5 mv/v vref input impedance vref_dis = 1 , vref = 1.3 v to 1.7 v 100 k vref output impedance vref_cal = 1, i load = 10 a, - 10 a 3.2 k vnom definition (see note 2 ) 2 )22 ( 1 )22 ( )22( )( 2 tc t tc t vref t vnom ? + ? + = v if temperature characterization trim information is not available (71m654 3f and 71m6543g ) vnom temperature coefficients : tc1 = tc2 = trimt ? ? 95.4 275 trimt ? ? ? 00028 .0 557 .0 v/c v /c 2 vref(t) deviation from vnom(t) (see note 1) : 62 10 )( )( )( 6 t vnom t vnom t vref ? - 40 +40 ppm /c vref aging 25 ppm / year notes: 1. guaranteed by design; not production tested. 2. this relationship describes the nominal behavior of vref at different temperatures, as governed by a second order polynomial of 1 st and 2 nd order coefficients tc1 and tc2. 3. for the parameters in this table, unless otherwise specified, vref_dis = 0 , pll_fast =1 downloaded from: http:///
71m6543f/71m6543g data sheet v2 141 6.4.15 adc converter table 103 : adc converter performance specifications p arameter c ondition m in t yp max unit recommended input range (vin - v3p3a ) - 250 250 mv peak voltage to current crosstalk ) cos( * 10 6 vcrosstalk vin vin vcrosstalk ? (see note 1) vin = 200 mv peak, 65 hz, on vadc8 (va) or vadc9 (vb) or vadc10 (vc) . vcrosstalk = largest mea surement on iadc0 - 1 or iadc2 - 3 or iadc4 - 5 or iadc6 -7 - 10 10 v/v input impedance , no pre - amp vin= 65 hz 40 90 k a dc gain error vs %power supply variation 3.3/ 3 3 100 / 357 10 6 a p v v nv nout in pk ? ? vin=200 mv pk, 65 hz v3p3a=3.0 v, 3.6 v 50 ppm / % input offset iadc0=iadc1=v3p3a iadc0=v3p3a diff0_e =1, pre_e =0 diff0_e =0 , pre_e =0 - 10 - 10 10 10 mv mv thd @ 250mvpk name fir_len adc_div pll_fast mux_div a 0 0 0 3 b 1 0 0 2 c 0 0 1 11 d 1 0 1 6 e 2 0 1 4 f 0 1 0 2 g 0 1 1 6 h 1 1 1 3 j 2 1 1 2 v in = 65hz, 250mvpk, 64kpts fft, blackman harris window . a b - 82 c d - 84 e f - 83 g h - 86 j a - 75 b - 75 c - 75 d - 75 e - 75 f - 75 g - 75 h - 75 j - 75 db thd @ 20mvpk name fir_len adc_div pll_fast mux_div a 0 0 0 3 b 1 0 0 2 c 0 0 1 11 d 1 0 1 6 e 2 0 1 4 f 0 1 0 2 g 0 1 1 6 h 1 1 1 3 j 2 1 1 2 v in = 65hz, 20mvpk, 64kpts fft, blackman harris window . a - 85 b - 91 c - 85 d - 91 e - 93 f - 85 g - 85 h - 91 j - 93 db lsb size : name fir_len adc_div pll_fast mux_div a 0 0 0 3 b 1 0 0 2 c 0 0 1 11 d 1 0 1 6 e 2 0 1 4 f 0 1 0 2 g 0 1 1 6 h 1 1 1 3 j 2 1 1 2 vin=65hz, 20mvpk, 64kpts fft, blackman - harris window a 3470 b 406 c 3040 d 357 e 151 f 3470 g 3040 h 357 j 151 nv digital full - scale: name fir_len adc_div pll_fast mux_div a 0 0 0 3 b 1 0 0 2 c 0 0 1 11 d 1 0 1 6 e 2 0 1 4 f 0 1 0 2 g 0 1 1 6 h 1 1 1 3 j 2 1 1 2 a: 91125 b: 778688 c: 103823 d: 884736 e: 2097152 f: 91125 g: 103823 h: 884736 j: 2097152 lsb downloaded from: http:///
71m6543f/71m6543g data sheet 142 v2 p arameter c ondition m in t yp max unit note: 1. guaranteed by design; not production tested. 2. unless stated otherwise, t he following test conditions apply to all the parameters provided in this table: fir_len[1:0] =1, vref_dis =0, pll_fast =1, adc_div =0, mux_div =6, lsb values do not include the 9 - bit left shift at ce input. 6.4.16 pre - amplifier for iadc0 - iadc1 table 104 : pre - amplifier performance specifications parameter condition min typ max unit differential gain vin=30mv differential vin=15mv differential (see note 1) t a = 5 ? c, v3p3=3.3 v, pre_e =1, fir_len =2, diff0 _e =1, 2520hz sample rate 7.8 7.8 7.92 7.92 8.0 8.0 v/v v/v gain variation vs v3p3 vin=30mv differential (see note 1) v3p3 = 2.97 v, 3.63 v - 100 100 ppm/% gain variation vs temp vin=30mv differential (see note 1) t a = - 40 ? c, 85 ? c 10 - 25 - 80 ppm/c phase shift, vin=30mv differential (see note 1) t a = 25 ? c, v3p3=3.3 v -6 6 mo preamp input current iadc0 iadc1 pre_e =1, fir_len =10, diff0_e =1 2520hz sample rate, iadc0=iadc1=v3p3 4 4 9 9 16 16 ua ua preamp+adc thd vin=30mv differential vin=15mv differential t a = 25 ? c, v3p3=3.3 v , pre_e =1, fir_len =2 , diff0 _e =1, 2520hz sample rate. - 82 - 86 db db preamp offset iadc0=iadc1=v3p3+30mv iadc0=iadc1= v3p3+15mv iadc0=iadc1= v3p3 iadc0=iadc1= v3p3 - 15mv iadc0=iadc1= v3p3 - 30mv t a = 25 ? c, v3p3=3.3 v, pre_e =1, fir_len =10, diff0 _e =1, 2520hz sample rate - 0.63 - 0.57 - 0.56 - 0.56 - 0.55 mv mv mv mv mv note: 1. guaranteed by design; not production tested. downloaded from: http:///
71m6543f/71m6543g data sheet v2 143 6.5 t iming s pecifications 6.5.1 flash memory table 105 : flash memory timing specifications p arameter c ondition m in t yp max unit flash write cycles - 40 c to +85 c 20,000 cycles flash data retention 25 c 85 c 100 10 years flash byte writes between page or mass erase operations 2 cycles write time per byte 21 s page erase (1024 bytes) 21 ms mass erase 21 ms 6.5.2 spi slave table 106 . spi slave timing specifications parameter condition min typ max unit spi setup time spi_di to spi_ck rise 10 ns spi hold time spi_ck rise to spi_di 10 ns spi output delay spi_ck fall to spi_d0 40 ns spi recovery time spi_csz fall to spi_ck 10 ns spi removal time spi_ck to spi_csz rise 15 ns spi clock high 40 ns spi clock low 40 ns spi clock freq spi freq/mpu freq 2.0 mhz/mhz spi transaction space spi_csz rise to spi_csz fall 4.5 mpu cycles 6.5.3 eeprom i nterface table 107 : eeprom interface timing p arameter c ondition m in t yp max unit write clock frequency (i 2 c) ckmpu = 4.9 mhz, using interrupts 310 khz ckmpu = 4.9 mhz, bit - banging dio2/3 pll_fast = 0 10 0 khz write clock frequency (3 - wire) ckmpu = 4.9 mhz pll_fast = 0 pll_fast = 1 160 500 khz downloaded from: http:///
71m6543f/71m6543g data sheet 144 v2 6.5.4 reset pin table 108 : reset pin timing p arameter c ondition m in t yp max unit reset pulse width 5 s reset pulse fall time (see note 1) 1 s note: 1. guaranteed by design; not production tested. 6.5.5 r eal - time clock (rtc) table 109 : rtc range for date p arameter c ondition m in t yp max unit range for date 2000 ? 2255 year downloaded from: http:///
71m6543f/71m6543g data sheet v2 145 6.6 100 - pin lqfp p ackage outline drawing controlling dimensions are in mm. figure 41 : 100 - pin lqfp package outline 1 15.7(0.618)16.3(0.641) 15.7(0.618)16.3(0.641) top view max. 1.600 0.50 typ. 14.000 +/- 0.200 0.225 +/- 0.045 0.60 typ> 1.50 +/- 0.10 0.10 +/- 0.10 side view downloaded from: http:///
71m6543f/71m6543g data sheet 146 v2 6.7 71m6543 pinout 1 71m6543f 71m6543g 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 91 92 93 94 95 96 97 98 99 100 26 27 28 29 30 51 52 53 54 55 56 57 58 59 60 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 segdio17 tmuxout/seg47 spi_di /segdio38 tx v3p3d segdio1 /vpulse segdio3 /sdata spi_csz/ segdio36 v3p3sys com1com2 com3 com0 segdio45 nc xingndd vbatice_e segdio52 opt_tx/segdio51 vadc9vadc10 v3p3agnda vadc8 pbvlcd test opt_rx/segdio55 iadc5 xout iadc0 iadc3iadc4 iadc1 iadc2iadc6 segdio27/com4 iadc7 spi_do /segdio37 segdio26/com5 segdio25segdio24 segdio23 segdio22 segdio21 segdio20 segdio19 segdio35segdio33 segdio32 segdio30 segdio29 segdio31segdio28 segdio34segdio18 gndavbat_rtc e_rxtx /seg48 e_tclk /seg49 e_rst /seg50 rxsegdio53 reset tmux2out/seg46 segdio44 segdio43 segdio42 segdio41 segdio40 spi_cki /segdio39 segdio16segdio15 segdio14 segdio13 segdio10 segdio11 segdio12 segdio9 segdio8/ di segdio7/ ypulse segdio6/ xpulse segdio5segdio4 segdio2 /sdck segdio0 /wpulse segdio54 vref ncnc nc nc vdd nc nc ncnc nc figure 42 : pinout for the l qf p- 100 package downloaded from: http:///
71m6543f/71m6543g data sheet v2 147 6.8 71m6543 pin d escriptions 6.8.1 71m6543 power and ground pins pin types: p = power, o = output, i = input, i/o = input/output . the circuit number denotes the equivalent circuit, as specified under section 6.8.4 i/o equivalent circuits . table 110 : 71m6543 power and ground pins pin name type circuit function 72, 80 gnda p analog g round . this pin should be connected directly to the ground plane. 62 gndd p digital ground . this pin should be connected directly to the ground plane. 85 v3p3a p analog power supply . a 3.3 v power supply should be connected to this pin. v3p3a must be the same voltage as v3p3sys. 69 v3p3sys p system 3.3 v s upply. this pin should be connected to a 3.3 v power supply. 61 v3p3d o 13 auxiliary v oltage o utput of the c hip. in mission mode, this pin is con nected to v3p3sys by the internal selection switch. in brn mode, it is internally connected to vbat. v3p3d is floating in lcd and sleep mode. a bypass capacitor to ground should not exceed 0.1 f. 60 vdd o output of the 2.5 v regulator. this pin is powered in msn and brn modes. a 0.1 f bypass capacitor to ground should be connected to this pin. 89 vlcd o output of the lcd dac. a 0.1 f bypass capacitor to ground should be connected to this pin. 70 vbat p 12 battery backup pin to support the battery modes (brn, lcd). a battery or super capacitor is to be connected between vbat and gndd. if no battery is us ed, connect vbat to v3p3sys. 71 vbat_rtc p 12 rtc and oscillator power supply. a battery or super - capacitor is to be connected between vbat and gndd. if no battery is used, connect vbat_rtc to v3p3sys. downloaded from: http:///
71m6543f/71m6543g data sheet 148 v2 6.8.2 71m6543 analog pins pin types: p = power, o = output , i = input, i/o = input/output . the circuit number denotes the equivalent circuit, as specified in section 6.8.4 . table 111 : 71m6543 analog pins pin name type circuit function 87 86 iadc0 iadc1 i 6 differential or single - ended analog line current sense inputs. these pins are voltage inputs to the internal a/d converter. typically, they are connected to the outputs of current sensors. unused pins must be connect ed to v3p3a . when configured as differential inputs (i.e., by setting the diffx_e control bits, where x = 0, 2, 4, 6) p in s are paired to form differential inputs pairs: iadc0 - iadc1, i adc2 -i adc3 , i adc4 -i adc5 , and iadc6 - iadc7. iadc2 - iadc3, iadc4 - iadc5, and iadc6 - iadc7 c an be configured for communication with the 71m6xx3 remote isolated sensor interface (i.e., by setting the rmtx_e control bits, where x = 2, 4, 6). when configured as remote sensor interfaces, these pins form balanced digital pairs for bidirectional digita l communications with a 71m6xx3 remote isolated sensor. 68 67 iadc2 iadc3 66 65 iadc4 iadc5 64 63 iadc6 iadc7 84 vadc8 (va) i 6 line voltage sense inputs. these pins are voltage inputs to the internal a/d converter. typically, they are connected to the outputs of resistor dividers. unused pins must be connected to v3p3a. 83 vadc9 (vb ) 82 vadc10 ( vc ) 88 vref o 9 voltage reference for the adc. this pin should be left unconnected (floating). 75 xin i 8 crystal inputs. a 32 khz crystal should be connected across these pins. typically, a 15 pf capacitor is also connected from xin to gnda and a 10 pf capacitor is connected from xout to gnda. it is important to minimize the capacitance between these pins. see the crystal manufacturer data sheet for details. if an external clock is used, a 150 mv (p - p) clock signal should be applied to xin, and xout should be left unconnected. 76 xout o downloaded from: http:///
71m6543f/71m6543g data sheet v2 149 6.8.3 71m6543 digital pins pin types: p = power, o = output, i = input, i/o = input/output, n/c = no connect. the circuit number denotes the equivalent circuit, as specified in section 6.8.4 . table 112 : 71m6543 digital pins pin name type circuit function 12 C 15 com 0C com 3 o 5 lcd common outputs . these four pins provide the select signals for the lcd display. 45 segdio0/wpulse i/o 3, 4, 5 multiple - use pins. configurable as either lcd segment driver or dio. alternative functions with proper selection of associated i/o ram registers are: segdio0 = wpulse (45) segdio1 = vpulse (44) segdio2 = sdck (43) segdio3 = sdata (42) segdio6 = xpulse (38) segdio7 = ypulse (3 7) segdio8 = di (36) unused pins must be configured as outputs or terminated to v3p3/gndd. 44 segdio1/vpulse 43 segdio2/sdck 42 segdio3/sdata 41 segdio4 39 segdio5 38 segdio6/xpulse 37 segdio7/ypulse 36 segdio8/di 35 C 27 segdio[9:17] 25 C 18 segdio[18:25] 11 C4 segdio[28:35] 99 C 94 segdio[40:45] 52 segdio52 51 segdio53 47 segdio54 17 segdio26/com5 i/o 3, 4, 5 multiple - use pins. configurable as either lcd segment driver or dio with alternative function (lcd common drivers). 16 segdio27/com4 3 spi_csz/segdio36 i/o 3, 4, 5 multiple - use pins. configurable as either lcd segment driver or dio with alternative function (spi interface). 2 spi_do/segdio37 1 spi_di/segdio38 100 spi_cki/segdio39 53 opt_tx/segdio51 i/o 3, 4, 5 multiple - use pins, configurable as either lcd segment driver or dio with alternative function (optical port/uart1) 46 opt_rx/segdio55 58 e_rxtx/seg48 i/ o 1, 4, 5 multiuse p ins . c onfigurable as either emulator port pins (when ice_e pulled high) or lcd segment drivers (when ice_e tied to gnd). 56 e_rst/seg50 57 e_tclk/seg49 o 4, 5 59 ice_e i 2 ice e nable. when zero, e_rst, e_tclk, and e_rxtx become seg50, seg49, and seg48 respectively. for production units, this pin should be pulled to gnd to disable the emulator port. 92 tmuxout/seg47 o 4, 5 multi ple -u se p in s. c onfigurable as either multiplexer/clock output or lcd segment driver using the i/o ram registers . 93 tmux2out/seg46 downloaded from: http:///
71m6543f/71m6543g data sheet 150 v2 pin name type circuit function 91 reset i 2 chip r eset . this input pin is used to reset the chip into a known state. for normal operation, this pin is pulled low. to reset the chip, this pin should be pulled high. this pin has an internal 30 a (nominal) current source pulldown . no external reset circuitry is necessary. 55 rx i 3 uart0 i nput. if this pin is unused it must be terminated to v3p3d or gndd. 54 tx o 4 uart 0 o utput 81 test i 7 enables production test . this pin must be grounded in normal operation. 90 pb i 3 pushbutton i nput. this pin must be at gndd when not active or unused. a rising edge sets the wf _pb flag. it also causes the part to wake up if it is in slp or lcd mode. pb does not have an internal pullup or pulldown resistor . 26, 40, 48, 49, 50, 73, 74, 77, 78, 79 nc n/c no connection. do not connect this pin . downloaded from: http:///
71m6543f/71m6543g data sheet v2 151 6.8.4 i/o equivalent circuits figure 43 : i/o equivalent circuits oscillator equivalent circuit type 8: oscillator i/o digital input equivalent circuit type 1: standard digital input or pin configured as dio input with internal pull - up gndd 110k v3p3d cmos input v3p3d digital input pin digital input type 2: pin configured as dio input with internal pull - down gndd 110k gndd cmos input v3p3d digital input pin digital input type 3: standard digital input or pin configured as dio input gndd cmos input v3p3d digital input pin cmos output gndd v3p3d gndd v3p3d digital output equivalent circuit type 4: standard digital output or pin configured as dio output digital output pin lcd output equivalent circuit type 5: lcd seg or pin configured as lcd seg lcd driver gndd lcd seg output pin to mux gnda v3p3a analog input equivalent circuit type 6 : adc input analog input pin comparator input equivalent circuit type 7: comparator input gnda v3p3a to comparator comparator input pin to oscillator gndd oscillator pin vref equivalent circuit type 9: vref from internal reference gnda v3p3a vref pin v2p5 equivalent circuit type 10: v2p5 from internal reference gndd v3p3d v2p5 pin vlcd equivalent circuit type 11: vlcd power gndd lcd drivers vlcd pin vbat equivalent circuit type 12: vbat power gndd power down circuits vbat pin v3p3d equivalent circuit type 13: v3p3d from v3p3sys v3p3d pin from vbat 10 10 downloaded from: http:///
71m6543f/71m6543g data sheet 152 v2 7 o rdering i nformation 7.1 71m6543 ordering guide r efer to the 71m6xxx d ata s heet for the 71m6xx3 ordering guide information. table 113 . 71m6 543 ordering guide part p art description (package, typ a ccuracy) flash size (kb) packaging order number package marking 71m654 3f 100 - pin lqfp lead (pb) - free, 0. 1% 64 bulk 71m654 3f- igt/f 71m654 3f- igt 71m654 3f 100 - pin lqfp le ad (pb) - free, 0. 1% 64 tape and reel 71m6543f - igtr/f 7 1m654 3f- igt 71m6543 g 100 - pin lqfp lead(pb) - free, 0. 1% 128 bulk 71m6543g - igt/f 71m654 3g- igt 71m654 3g 100 - pin lqfp le ad(pb) - free, 0. 1% 128 tape and reel 71m6543g - igtr/f 7 1m654 3g- igt 8 related information the following documents related to the 71m6543 and 71m6xx3 are available: ? 71m6543 f/ 71m6543g data sheet ( this document) ? 71m6xxx data sheet ? 71m654 x software users guide (sug) ? 71m6543 demo board users manual (dbum) 9 contact information for technical support or more information about maxim products , contact technical support at www.maximintegrated.com/support . downloaded from: http:///
71m6543f/71m6543g data sheet v2 153 a ppendix a: acronyms afe analog front - end amr automatic meter reading ansi ameri can national standards institute ce compute engine dio digital i /o dsp digital signal processor fir finite impulse response i 2 c inter - ic bus ice in - circuit emulator iec international electrotechnical commission mpu microprocessor unit (cpu) pll phase -l ocked l oop rms root mean square sfr special function register soc system - on - chip spi serial peripheral interface tou time of use uart universal asynchronous receiver/transmitter downloaded from: http:///
71m6543f/71m6543g data sheet maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product . no circuit patent licenses are implied. maxim integrated reserves the right to c hange the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteris tics table are guaranteed. other parametric values quoted in t his data sheet are provided for guidance. maxim integrated products, 160 rio robles, san jose, ca 95134 usa 1 - 408 - 601 - 1000 ? 2013 maxim integrated products maxim integrated and the maxim integrated logo are trade marks of maxim integrated products, inc. appendix b : revision history revision number revision date description pages changed 1.0 1/1 1 initial release 1.1 3/11 added the 71m6543g, 71m6543gh all 1.2 4/11 removed the 17mw typ consumption at 3.3v for sleep mode from the features section 1 2 10/13 removed the 71m6543h , 71m6543gh ; updated pls_inv description on table 7 0 , added warning note on spi flash mode section, updated ien0 bit function and external mpu interrupts table, removed info_pg from the register map, changed ceconfig bit 23 to reserved, cor rected spi slave port diagram (figure 23), updated the text description of the signal input pins section, combined columns 3 and 4 of table 3 3 , updated the interrupt structure diagram, corrected the opt_txe active definition, updated the required ce code and settings notes about mux_div[3:0], added a note about v_ang_cnt under table 8 2 all downloaded from: http:///

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